Harlan Sur
VLSI Technology
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Publication
Featured researches published by Harlan Sur.
international reliability physics symposium | 1998
Subhas Bothra; Harlan Sur; V. Liang
The tungsten filled via plug process is commonly used in sub-half micron CMOS process technologies. As process technologies shrink beyond the 0.25 /spl mu/m generation, the metal overlap over the via also reduces. This results in vias which are not fully covered by the overlying interconnect lines. In the evaluation of such structures, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures.
international interconnect technology conference | 1998
Subhas Bothra; G.A. Rezvani; Harlan Sur; M. Farr; Jayarama N. Shenoy
The charge based capacitance measurement (CBCM) technique (Chen et al, IEDM p. 69, 1996) was used in order to measure femto-farad level intermetal capacitances between metal lines in different configurations. The results are presented and compared with the calculated numbers using the Rafael simulation program. These structures are used to evaluate the impact of process changes such as the use of low k dielectric on parasitic interconnect capacitance. The parasitic capacitances are determined by using a variety of interconnect structures with varying line width and spacing. Such measurements with low k materials show that the formation of these materials in small narrow spaces may be quite different from that in wide open areas.
Microelectronic device technology. Conference | 1998
Faran Nouri; Olivier Laparra; Harlan Sur; Samar K. Saha; Dipankar Pramanik; Martin Manley
An integrated shallow trench isolation process utilizing HDP (High Density Plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 micrometer technologies.
Archive | 1997
Harlan Sur; Subhas Bothra; Xi-Wei Lin; Martin Manley; Robert Payne
Archive | 1998
Harlan Sur; Subhas Bothra; Xi-Wei Lin; Martin Manley; Robert Payne
Archive | 1999
Harlan Sur
Archive | 1997
Harlan Sur; Olivier Laparra; Dipankar Pramanik
Archive | 1997
Harlan Sur; Subhas Bothra
Archive | 1997
Harlan Sur; Subhas Bothra
Archive | 1997
V. Liang; Subhas Bothra; Harlan Sur