Subodh M. Reddy

Clock Distribution Architectures: A Comparative Study

This paper evaluates and compares different clock architectures such as mesh, tree and their hybrids, on several industrial designs. The goal of our study is to gain a quantitative understanding of engineering trade-offs between different architectures with respect to clock skew, latency, timing uncertainty, and power. This understanding will lead to guidelines for determining the best clock architecture for the design specification and constraints. To the best of our knowledge, no work has been published on evaluating and comparing these architectures on real industrial designs. Our study shows that mesh-based architectures are better than tree architectures for skew (< 1ps skew) and are more robust to variations (18% reduction in timing uncertainty as compared to tree). The power penalty associated with a mesh as compared to a tree was found to be between 10-40%. Use of multiple meshes can help reduce the power penalty

Analyzing Timing Uncertainty in Mesh-based Clock Architectures

Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations between signal nodes spatially distributed over the chip. However, one problem with the mesh architectures is the difficulty in accurately analyzing large instances. Furthermore, variations in process and temperature, supply noise and crosstalk noise cause uncertainty in the delay from clock source to flip-flops. In this paper, we study the problem of analyzing timing uncertainty in mesh-based clock architectures. We propose solutions for both pure mesh and (mesh + global-tree) architectures. The solutions can handle large design and mesh instances. The maximum error in uncertainty values reported by our solutions is 1-3ps with respect to the golden Monte Carlo simulations, which is at most 0.5% of the nominal clock latency of about 600ps

A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.

Sensitivity-based modeling and methodology for full-chip substrate noise analysis

Substrate noise (SN) is an important problem in mixed-signal designs. With increasing design complexity, it is not possible to simulate for SN with a detailed SPICE model that uses an accurate model for each transistor. In this paper, we propose a sensitivity analysis- and static timing analysis-based methodology to derive a reduced model that computes the worst case substrate noise in the design. The reduced model contains only passive components, which are very few, and is very quick to simulate. The main feature of our methodology is that, unlike previous approaches, it is independent of input patterns and does not need to simulate for millions of clock cycles. This lets us apply it to a full-chip design in reasonable CPU time. We validate our reduced model on several benchmark circuits against a detailed and highly accurate reference model. On average, the reduced model is within 16.4% of the reference model and is up to 38 times faster. Finally, we apply our methodology to a mixed-signal switch chip design consisting of 8 million gates and show that it finishes in 17 minutes.

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel

In multi-Gb/s wireline communications, equalizers are used to compensate for channel-induced signal distortion in order to stretch the maximum distance of transmission. Both amplitude and phase can be distorted in a channel. Amplitude distortion is a frequency-dependent attenuation due to skin effect and dielectric loss, causing inter-symbol-interference (ISI). A transmitter (TX) discrete-time pre-emphasis (PE) filter, a receiver (RX) continuous-time Linear Equalizer (LE), and an RX Decision-Feedback Equalizer (DFE) are generally used to cancel ISI. At 10Gb/s or higher data rate, equalizers for up to 33 to 39dB Nyquist loss and up to 20 to 25dB adapted loss range were reported [1–3]. On the other hand, how to compensate phase distortion is not clearly understood in practical circuit design. Theoretically, if a channel has minimum-phase-likecharacteristics, phase distortion is automatically co-equalized with amplitude distortion by a minimum-phase equalizer [4]. While this is the case for high-speed cables [5], it is not for PCB traces, because a non-minimum-phase equalizer, e.g., a PE with a pre-cursor tap, produces lower BER over a high-loss PCB channel than a minimum-phase equalizer, e.g., a PE without a pre-cursor tap. Thus the IEEE 10Gb Ethernet standard for backplanes adopted 3-tap PE with a precursor tap [6]. However, adaptive phase equalization in hardware has not been reported in the literature.

Accurate substrate noise analysis based on library module characterization

As the design complexity increases, a detailed SPICE model cannot be used to study substrate noise injected by the digital logic into the analog circuit in a mixed-signal system. Hence a reduced yet accurate model is needed. Previous work shows that the current drawn by the digital circuit from the power supply has a big impact on the substrate noise and therefore must be modeled accurately in the reduced model. In this paper, we propose an accurate current modeling technique based on pre-characterizing library modules for the current drawn from the power supply as a function of time, load capacitance, input transitions and slews. This technique is then embedded in both pattern-dependent (PDM) and pattern-independent (PIM) substrate noise analysis methodologies. Results on several gate-level benchmarks show that the proposed scheme is, on average, within 4.5% of the detailed BSIM3-based model for PDM and within 12% for PIM. In contrast, the previously proposed scheme of (Murgai et al., 2004) has an average discrepancy of 176% with the detailed model for PIM.