Sudhakar Bobba

Simulation and optimization of the power distribution network in VLSI circuits

In this paper, we present simulation techniques to estimate the worst-case voltage variation using an RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequency-domain steady-state simulation of the linear RC circuit to evaluate the worst-case instantaneous voltage drop for the RC power distribution networks. The proposed technique unlike existing techniques, is guaranteed to give the maximum voltage drop at nodes in the RC power distribution network. We present experimental results to compare the frequency-domain and time-domain simulation techniques for estimating the maximum instantaneous voltage drop. We also present frequency domain sensitivity analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network. Experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques.

Maximum leakage power estimation for CMOS circuits

Low supply voltage requires the device threshold to be reduced in order to maintain performance. As the device threshold voltage is reduced, it results in an exponential increase of leakage current in the subthreshold region. The leakage power is no longer negligible in such low voltage circuits. Estimates of maximum leakage power can be used in the design of the circuit to minimize the leakage power. The leakage power is dependent on the input vector. This input pattern dependence of the leakage power makes the problem of estimating the maximum leakage power a hard problem. In this paper, we present graph based algorithms for estimating the maximum leakage power. These algorithms are pattern-independent and do not require simulation of the circuit. Instead the circuit structure and the logic functionality of the components in the circuit are used to create a constraint graph. The problem of estimating the maximum leakage power is then transformed to an optimization problem on the constraint graph. Efficient algorithms on the graph are used to estimate the maximum leakage power dissipated by a circuit. We also present comparisons with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuits to verify the accuracy of the method.

IC power distribution challenges

With each technology generation, delivering a time-varying current with reduced nominal supply voltage variation is becoming more difficult due to increasing current and power requirements. The power delivery network design becomes much more complex and requires accurate analysis and optimizations at all levels of abstraction in order to meet the specifications. We describe techniques for estimation of the supply voltage variations that can be used in the design of the power delivery network. We also describe the decoupling capacitor hierarchy that provides a low impedance to the increasing high-frequency current demand and limits the supply voltage variations. Techniques for high-level power estimation that can be used for performance vs. power trade-offs to reduce the current and power requirements of the circuit are also presented.

Static timing analysis including power supply noise effect on propagation delay in VLSI circuits

This paper presents techniques to include the effect of supply voltage noise on the circuit propagation delay of a digital VLSI circuit. The proposed methods rely on an input-independent approach to calculate the logic gates worst-case power supply noise. A quasi-static timing analysis is then applied to derive a tight upper-bound on the delay for a selected path with power supply noise effects. This upper-bound can be further reduced by considering the logic constraints and dependencies in the circuit. Experimental results for ISCAS-85 benchmark circuits are presented using the techniques described in the paper. HSPICE simulation results are also used to validate our work.

Estimation of maximum current envelope for power bus analysis and design

In this p ap er we pr esent an inputpattern independent method to compute the maximum current envelope, which is an upper bound over all possible curr ent waveforms drawn by a circuit. The maximum current envelope can be used to compute the worst-c ase RMS current and average cur rent dr awn by a set of gates. These current values can be used in the design of the p ower bus to ensure that the power bus interconne cts are not susc eptible to ele ctromigration (EM) induced failur e. We also present comparisons with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuits to verify the accuracy of the method.

Current-mode threshold logic gates

In this paper, we present low-power and high-performance logic gates called the current-mode threshold logic (CMTL) gates. Low-power dissipation is achieved by limiting the voltage swing on the interconnects and the internal nodes of the CMTL gates. High-performance is achieved by the use of transistor configurations that sense a small difference in current and set the differential outputs to the correct values. The realization of NAND, NOR, AND, OR logic gates and other logic functions using the CMTL gates is presented. We also present several implementations of CMTL gates and describe the relative advantages and limitations of these implementations. SPICE simulation, results for a 1.5 V 0.18 u CMOS technology are also presented for the different circuit configurations described in the paper.

Design of dynamic circuits with enhanced noise tolerance

In this paper, we present a design technique that increases the noise tolerance of dynamic circuits. We present a low-noise circuit which has very low leakage and variable input noise margin. This circuit can be used in the design of noise-tolerant dynamic wide-OR gates which are otherwise extremely vulnerable to noise at the inputs and charge leakage from the dynamic evaluation node. High speed decoders and comparators used in a cache can be realized using dynamic wide-OR gates. We present simulation results to demonstrate the effectiveness of the proposed design technique compared to other techniques. We also present the application of the low-noise circuit to enhance the noise immunity of dynamic SOI gates against parasitic bipolar leakage.

Analytical expressions for average bit statistics of signal lines in DSP architectures

Accurate high-level power estimation methods are required for exploring the design space to obtain an, optimal low-power circuit. DSP architectures are regular and they consist of interconnected macro-blocks such as adders and multipliers. Previously the power dissipation of macro-blocks was related to the average bit statistics. Given the input word-level statistics for a DSP architecture, the word-level statistics at all the internal signal lines can be computed analytically using transfer function evaluation or by propagating the statistics. In this paper, we present simple analytical expressions for computing the average bit statistics using the word-level statistics of the signal lines in a DSP architecture.

Analytical expressions for power dissipation of macro-blocks in DSP architectures

Power minimization is an important objective in present day VLSI design. Macromodels for power dissipation can be used to estimate power at a high-level of abstraction. High-level power estimation methods provide the designer with more flexibility to explore design trade-offs early in the design cycle. In this paper, we present closed-form analytical expressions for power consumption of macro-blocks in terms of the word-statistics. We present an analytical expression for total bit transition activity of a signal line in terms of the word-statistics. We also present analytical power models for macro-blocks in DSP architectures in terms of total bit transition activity and other parameters. Experimental results validating the analytical expressions are also included in this paper.

Simultaneous switching noise in CMOS VLSI circuits

In this paper, we present techniques for estimating the worst-case voltage variations in the power distribution network due to switching of I/O buffers or internal logic circuits in a small time interval. We refer to these voltage variations as the simultaneous switching noise (SSN). We present simulation results to show that a relative skew in the switching time can dramatically increase the SSN due to I/O buffers with dissimilar loads. We also present a constraint graph based technique that accounts for logic dependencies between switching elements to obtain accurate estimates of the worst-case SSN due to internal logic circuits. Comparisons with SPICE simulations are presented to validate our approach.