Sudhir M. Gowda

Design and characterization of analog VLSI neural network modules

A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 mu m double-polysilicon CMOS technologies are presented to demonstrate the testing procedure. >

Advanced integrated-circuit reliability simulation including dynamic stress effects

A systematic approach to predict semiconductor degradation effects using reliability simulation is described. The DC degradation monitor is first extracted during transient circuit simulation. An AC degradation factor is then used to determine circuit performance degradation. By using these techniques on the design of CMOS components, proper long-term reliability can be achieved for high-speed circuits. Experimental results on digital circuits using an industrial submicrometer technology demonstrate the effectiveness of this approach in reliable VLSI circuit design. Results on two-input NAND gates, DRAM precharging circuit, and SRAM control circuits are presented. >

Design of reliable VLSI circuits using simulation techniques

An iterative simulation method of predicting the impact of progressive device degradation on circuit performance due to common microelectronic failure mechanisms is described. Simulation schemes for the lifetime prediction of ASICs as well as modeling requirements for accurate and efficient simulation are presented. These simulation schemes have been implemented in the prototype reliability simulator RELY to evaluate circuit performance degradation and provide reliability enhancement information. Hot-carrier effects on submicrometer digital and analog circuits are used to demonstrate the approach. Experimental results on precharging circuitry for sense amplifiers and operational amplifiers are presented. >

BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits

The BSIM plus MOS transistor model is developed for simulation of digital and analog VLSI circuits in advanced submicron technologies. A compact parameter set is carefully selected to accurately characterize transistors and achieve continuity of the drain current and its derivatives across the different regions of operation. Several submicron modeling techniques are described. Simulated results agree well with measured data of transistors from two industrial technologies. >

Testing of analog neural array-processor chips

A systematic approach to test analog array-processor neural chips is presented. Unique testing problems for analog neural chips are described and effective solutions are discussed. Based on the hierarchical methodology, testing of analog array-processor neural chips can be systematically addressed. The test results for programmable analog neural chips fabricated by a 2- mu m CMOS process are presented. These chips contain 25 neurons and 1600 synapses.<<ETX>>

VLSI circuit design with built-in reliability using simulation techniques

The use of reliability assurance and enhancement of integrated circuits in the design of high-performance electronic systems is discussed. Circuit simulators with embedded degradation models can be utilized to accurately predict VLSI reliability due to hot-carrier effects and electromigration. Basic design methods for constructing digital and analog circuit blocks with adequate built-in reliability are presented. Lifetime for DRAM circuitries and operational amplifiers can be significantly increased through these novel simulation techniques. Several practical VLSI design examples using an integrated-circuit reliability simulator are discussed.<<ETX>>

Explicit geometry dependence of MOS transistor parameters by the pseudoboundary method

The pseudoboundary method is an engineering technique to extend the use of a single parameter set over the entire geometric design space for VLSI circuits. The technique eliminates adverse effects, such as negative output conductance, by clamping the evaluation of geometric dependence terms at the systematically determined boundaries of a primary region. The use of this technique is essential for accurate simulation of analog and digital circuits as well as prediction of circuit performance using next-generation submicron VLSI fabrication technologies. Results demonstrating the effectiveness of the technique using the widely accepted Berkeley short-channel IGFET model (BSIM) are presented, with data from transistors of different geometries ranging from 0.5 to 70 μm.

Advanced VLSI circuit simulation using the BSIM

The BSIM plus model, a significantly enhanced version of the widely used BSIM (Berkeley short-channel insulated-gate FET model), is presented. The model uses a compact set of 21 parameters to provide accurate drain current expressions in sub-half-micron transistors. The performance of the model has been demonstrated on several common circuit building blocks, as well as in recently reported innovative circuits such as self-timed circuits. Simulation results on operational amplifier, DRAM (dynamic random-access memory), self-timed adder, and band-gap reference circuits are presented. The model has been implemented in modified versions of the SPICE circuit simulation program and SUXES parameter extraction program.

Fully automated layout generators for high-performance analog VLSI modules

Algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layout generation. A new method to incorporate integrated-circuit reliability simulation results into the performance-driven optimization step is also presented. Experimental results on operational amplifiers, voltage comparators, and voltage-controlled oscillators show that the new generation program can produce high-quality circuit layouts efficiently.<<ETX>>

Testing Of Programmable Analog Neural Network Processors

Artificial neural networks are capable of high-speed com- putation to solve many complex problems in scientific and engineering applications. A systematic method to test large arrays of analog, digital, or mixcd-signal circuit components that constitute these networks is describcd. The testing procedure consists of a parametric test and a behavioral test. Characteris- tics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Several measurement results from neural network chips are presented to demonstrate the testing procedure. into the current mirror which is used to bias the synapse circuit. The synapsc is fully programmable, with the analog weight being stored on a DRAM-style capacitor which is addressed by using row and column decoders. The synapse circuit is a transconduc- tance amplifier. The synapse weight voltage, Vprog, determines the synapse output current, Id. The summed synapse output current drives the output neuron circuit. The output neuron is a two-stage operational amplificr with adjustable gain. The gain control is achieved by changing the bias of an NMOS transistor that is connected in the feedback loop of the amplifier. The schematic of a different implementation of input neuron, synapse and output neuron circuits is shown in Fig. 4. The input ncuron consists of an operational amplifier connected as a unity- gain buffer. The synapse circuit is made up of a modified Gilbert multiplier (lo) with low lincarity error over a wide dynamic range. The synapse weight is stored in a differential format in order to improve the accuracy of the weighted multiplication operation. In the output neuron, currents from the synapses that are connected to it are summcd and hen converted into a voltage by an I-V con- verter circuit. The output neuron also contains buffers with active feedback resistors in order to implement a sigmoid function with a controllable voltage gain. A winncr-take-all circuit is used to select the largest output when a self-organizing neural network chip is designed.