Ji-Chien Lee

VLSI neuroprocessors for video motion detection

The system design of a locally connected competitive neural network for video motion detection is presented. The motion information from a sequence of image data can be determined through a two-dimensional multiprocessor array in which each processing element consists of an analog neuroprocessor. Massively parallel neurocomputing is done by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is performed by using an analog point-to-point interconnection scheme. To maintain strong signal strength over the whole system, global data communication between the host computer and neuroprocessors is carried out in a digital common bus. A mixed-signal very large scale integration (VLSI) neural chip that includes multiple neuroprocessors for fast video motion detection has been developed. Measured results of the programmable synapse, and winner-takes-all circuitry are presented. Based on the measurement data, system-level analysis on a sequence of real-world images was conducted.

SLAM: a smart analog module layout generator for mixed analog-digital VLSI design

A tool for the smart layout of analog modules, which aims to provide a flexible analog layout solution for the mixed analog-digital VLSI design environment, is described. New algorithms have been developed for novel primitive cell recognition, intelligent layout and detail routing, and performance-driven optimization. Software implementation and experimental results on several analog VLSI modules such as operational amplifiers and voltage-controlled oscillators are presented.<<ETX>>

A nonvolatile analog neural memory using floating-gate MOS transistors

Simple floating-gate transistors fabricated by a conventional double-polysilicon process show excellent programming and charge-retention characteristics. A five-transistor synapse cell achieves 8-bit resolution and at least 6-bit accuracy for analog neural computation. It occupies 67 μm×73 μm in a 2-μm CMOS process and can retain charge accuracy for over 25 years.

Parallel digital image restoration using adaptive VLSI neural chips

Real-time digital image restoration using massively parallel Hopfield neural chips is presented. An efficient mixed-signal VLSI design with analog circuitry to perform neural computation and digital circuitry to process multiple-bit pixel information greatly reduces the network size. Analog programmable synapse cells of 8 bit accuracy are dynamically refreshed. The gain-adjustable neurons enable electronic annealing to quickly reach global minimum in energy function. A prototype 25-neuron chip occupies a silicon area of 4.6*6.8 mm/sup 2/ in MOSIS 2- mu m CMOS process has been designed and tested. The speedup factor for each chip is 90 compared to the Sun-3 workstation. An 100-neuron image-restoration chip is achievable in the industrial-level 1- mu m technologies.<<ETX>>

A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture

An analog computing-based systolic architecture which employs multiple neuroprocessors for high-speed early vision processing is presented. For a two-dimensional image, parallel processing is performed in the row direction and pipelined processing is performed in the column direction. The mixed analog/digital design approach is suitable for implementation of electronic neural systems. Local data computation is executed by analog circuitry to achieve full parallelism and to minimize power dissipation. Inter-processor communication is carried out in the digital format to maintain strong signal strength across the chip boundary and to achieve direct scalability in neural network size. For demonstration purposes, a compact and efficient VLSI neural chip that includes multiple neuroprocessors for high-speed digital image restoration is designed. Measured results of the programmable synapse, and statistical distribution of measured synapse conductances are presented. Based on these results, system-level analyses at 8-bit resolution are conducted. A 8.0×6.0-mm2 chip from a 1.2-µm CMOS technology can accommodate 5 neuroprocessors and the speed-up factor over the Sun-4/75 SPARC workstation is around 450. This chip achieves 18 Giga connections per second.

A mixed-signal VLSI neuroprocessor for image restoration

An analog systolic architecture that uses multiple neuroprocessors for image restoration is presented. For a two-dimensional image, parallel processing is performed for different rows of pixel data and pipelined processing is performed on each row of pixel data. For the image restoration neuroprocessor, local data computation is executed by analog circuitry to achieve full parallelism and to minimize power dissipation. Interprocessor communication is carried out in the digital format to maintain strong signal strength across the chip boundary and to allow multichip operation for high-speed image processing. >

Real-time computing of optical flow using adaptive VLSI neuroprocessors

The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2- mu m CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips.<<ETX>>

Fully automated layout generators for high-performance analog VLSI modules

Algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layout generation. A new method to incorporate integrated-circuit reliability simulation results into the performance-driven optimization step is also presented. Experimental results on operational amplifiers, voltage comparators, and voltage-controlled oscillators show that the new generation program can produce high-quality circuit layouts efficiently.<<ETX>>

A mixed-signal VLSI competitive neuroprocessor for video motion detection

VLSI design of a competitive neural network for video motion detection is presented. Massively parallel neurocomputing is performed by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is carried out by using an analog point-to-point interconnection scheme, while global data communication between the host computer and neuroprocessors is achieved through a digital common bus. Experimental results of the analog circuit blocks and system-level analysis on a sequence of real-world images are also presented.

Multiprocessor-based video motion detection using adaptive neural systems

Fast motion detection is an important step in the high-speed video/vision processing systems. System-level design of a 2-dimensional mesh-concerned competitive neural network for video motion detection is presented. The motion information from a sequence of images can be obtained through mixed-analog/digital signal processing. Massively parallel neurocomputing is performed by multiple copies of compact and efficient neuroprocessors. Inter-processor data transfer is carried out by dedicated point-to-point analog interconnections. Global data communication between the host computer and neuroprocessors is through the digital common bus to maintain strong signal strength. An extendable analog winner-take-all circuit is used to implement the competition function with a minimal delay time. A 1.5*2.8-cm/sup 2/ chip in a 1.2- mu m CMOS technology can accommodate 64 velocity-selective neuroprocessors. This chip can achieve 83.2 Giga-connections per second. By using 128 VLSI neural chips, the speed-up factor over the Sun-4/60 SPARC station-1 is estimated to by 54545.<<ETX>>