Sujata Sen

Two-dimensional C-V model of AlGaAs/GaAs modulation doped field effect transistor (MODFET) for high frequency applications

This paper reports a detailed two-dimensional (2-D) analytical capacitance-voltage (C-V) model for a modulation-doped field effect transistor. The contribution of various capacitances on the performance of the device is shown. The analysis includes the effect of design parameters on cutoff frequency, and the peak cutoff frequency obtained is 190 GHz. The excellent agreement with the simulated and experimental data proves the validity and applicability of the model to optimize the device at high frequencies.

Thermal characterization of a double-gate silicon-on-insulator MOSFET

A two-dimensional analytical model to study the behaviour of the device parameters in various temperature ranges is developed. The temperature dependences of the threshold voltage, drain current and channel transconductance are modelled using temperature-sensitive parameters. The effects of temperature on the cut-off frequency and channel-transit time are also discussed. The results so obtained are compared with the experimental data for a single-gate silicon-on-insulator MOSFET.

Temperature and aluminium composition dependent sheet carrier concentration at AlGaAs/GaAs interface

The sheet carrier concentration (two-dimensional electron gas (2DEG), at the AlGaAs/GaAs interface is analytically modelled with its dependence on temperature (from liquid nitrogen temperature to room temperature and higher) and aluminium composition, at equilibrium and for charge control by the gate. The effect of deep-donor concentration is also taken into account and a decrease in the 2DEG is observed at higher concentrations of deep donors and at higher temperatures. The theoretical analysis, based on Fermi-Dirac statistics, shows that the thermal characterization of the 2DEG is essential. The results obtained are compared with experimental data.

An analytical 2D model for drain-induced barrier lowering in subquarter micrometer gate length InAlAs/InGaAs/InAlAs/InP LMHEMT

This paper presents an analytical 2D model for InAlAs/InGaAs/InAlAs/InP LMHEMT that explains the drain induced barrier lowering (DIBL) and its effect on the device performance. The increasing drain voltage lowers the potential barrier between source and drain in or near the subthreshold region. As the barrier is lowered to be comparable to the thermal energy the device begins to conduct again. This effect causes the threshold voltage control problem and degrades the device performance. The model is used to obtain the potential distribution and the electric field in the depletion region and the threshold voltage is also calculated from the minimum channel potential. It is proposed as a consequence of the analysis that the device degradation due to DIBL effect is a very short channel problem.

A quasi two-dimensional analytical model for threshold voltage of a modulation doped field effect transistor

A two-dimensional analytical model for the threshold voltage of a subquarter-micrometer-gate Modulation Doped Field Effect Transistor (MODFET) is reported. The threshold voltage variation is obtained in terms of different device parameters. A very small shift in threshold voltage was observed supporting that the model suffers less from severe short channel effects. The model agrees well with the experimental data.

Current-voltage characteristics and small signal parameters of an AlGaAs/GaAs modulation doped field effect transistor

The results of an analysis based on the solution of the two-dimensional Poissons equation are presented to investigate the dependence of device characteristics and small signal parameters on biasing conditions and physical effects of geometry. Capacitance-voltage characteristics are also discussed with the inclusion of fringing capacitances. A maximum frequency of 177GHz is obtained and the results show close agreement with the experimental data.

Design Aspects of a Submicrometer Gate Length High Electron Mobility Transistor

An optimized model based on the solution of two-dimensional Poissons equation with improved performance for design aspect of a submicron gate length device is proposed. It analyses the dependence of threshold voltage on the process parameters and gives an idea about the choice of the doping concentration and AIGaAs layer thickness to obtain a minimum threshold voltage variation. The model discusses the different short channel parameters with their effect on the subthreshold current. When calculated results from the present model are compared with available experimental aata, a close agreement between the two is observed, thereby, confirming the validity of the model.