Wazir Singh

Energy efficient acquisition and reconstruction of EEG signals

In Wireless Body Area Networks (WBAN) the energy consumption is dominated by sensing and communication. Previous Compressed Sensing (CS) based solutions to EEG tele-monitoring over WBANs could only reduce the communication cost. In this work, we propose a matrix completion based formulation that can also reduce the energy consumption for sensing. We test our method with state-of-the-art CS based techniques and find that the reconstruction accuracy from our method is significantly better and that too at considerably less energy consumption. Our method is also tested for post-reconstruction signal classification where it outperforms previous CS based techniques. At the heart of the system is an Analog to Information Converter (AIC) implemented in 65nm CMOS technology. The pseudorandom clock generator enables random under-sampling and subsequent conversion by the 12-bit Successive Approximation Register Analog to Digital Converter (SAR ADC). AIC achieves a sample rate of 0.5 KS/s, an ENOB 9.54 bits, and consumes 108 nW from 1 V power supply.

Energy Efficient and Congestion-Aware Router Design for Future NoCs

Network-on-Chip (NoC) has been well accepted for energy efficient on-chip communications for many-core systems. But, a NoC router consumes significantly high power and the number of routers increases linearly with number of cores. For large scale applications, the cumulative power dissipation in routers is comparatively high. Of all router components, input buffers consume significant amount of power. Additionally, removing buffers from NoC router leads to performance degradation and network congestion overhead. To make NoC energy efficient without increasing network congestion, in this paper we approach the router architecture by utilizing the Marching Memory buffers instead of traditional register based buffers for better energy efficiency and performance. Energy analysis on a 16-core mesh based NoC topology running PARSEC and SPLASH-2 benchmark application traffic shows that in the presence of Marching Memory buffer, our proposed router reduces the total energy by 18% and 25% respectively with negligible performance overhead.

A proposed low-offset sense amplifier for SRAM applications

Random variations play a critical role in determining SRAM yield, by affecting both the bitcell and the read Sense Amplifiers (SA). A low-offset sense amplifier capable of static random access memory (SRAM) applications has been presented in this work. Simulated results show that the proposed sense amplifier has very low offset of 31.284 mV compared to the conventional sense amplifiers.

High resolution, high speed and low power comparator for high speed ADCs

A high-speed CMOS comparator with preamplifier and compare-latch circuit designed in UMC 0.18μm CMOS process with 1.8V power supply has been presented in this paper. It is a suitable choice for high speed flash-type ADCs. The comparator gives a resolution of 0.1mV at 500MHz with a power dissipation of 175 μW.

Biopotential acquisition unit for energy-efficient wearable health monitoring

In wearable health monitoring system, the energy consumption is dominated by the transmitter. These systems generally use proprietary acquisition platforms that are incompatible with each other which makes this even more challenging. This study presents a compressive sensing-based biopotential acquisition unit to reduce the overheads of wirelessly transmitting and storing the data. The instrumentation amplifier (INA) in the system defines the quality of the acquired biopotential signals. At the heart of the system is an analogue-to-information converter (AIC) to enable the random under-sampling operation. AIC is used to digitise the output of the biopotential INA. Both INA and AIC are implemented in 65 nm CMOS technology. To confirm stable operation under different operating conditions, the design is simulated under different process, voltage and temperature (PVT) corners. The simulation results show that the proposed INA has a common mode rejection ratio of 100.18 dB and noise of 35.89 pV/sqrt (Hz). AIC achieves a sampling rate of 0.5 kS/s, an effective number of bits 9.54 bits, figure of merit 187 fj/conv-step, and consumes 69.33 nW from 1 V power supply.

Energy efficient biopotential acquisition unit for wearable health monitoring applications

This paper presents a biopotential acquisition unit with an instrumentation amplifier and analog-to-information converter for wearable health monitoring applications. The instrumentation amplifier defines the quality of the acquired biopotential signals. At the heart of the system is an Analog to Information Converter (AIC) to enables the random under-sampling operation. AIC is used to digitize the output of the biopotential instrumentation amplifier. Both instrumentation amplifier and AIC are implemented in 65nm CMOS technology. The simulation results show that the proposed instrumentation amplifier has a CMRR of 100.18 dB and noise of 35.89nV/sqrt (Hz). AIC achieves a sampling rate of 0.5 KS/s, an ENOB 9.54 bits, FOM 187 fj/conv-step and consumes 69.66 nW from 1 V power supply.

SAR Analog to Digital Converter for bio-potential signals: A review

Monitoring of biopotential signals is very crucial in health care systems. With the development of recent CMOS technologies, it is possible to design biomedical ICs for these systems. The fully utilization of energy without sacrificing the performance is desirable for long life of such systems. A large number of systems are built on the basis efficient power consumption in biomedical applications recent days. The SAR ADC is a major part of these systems. This paper reviews different techniques used for design of low power SAR ADC by considering comparator, Sample & hold and DAC as variable components for reducing the power consumption and area.