Sujith Subramanian

N-channel InGaAs field-effect transistors formed on germanium-on-insulator substrates

InGaAs n-channel metal oxide semiconductor field-effect transistors (MOSFETs) were fabricated on germanium-on-insulator (GeOI) substrate for the first time. Integration of InGaAs on a GeOI substrate was achieved using a molecular beam epitaxy (MBE)-grown InAlAs graded buffer. The fabricated MOSFET, with a self-aligned Ni–InGaAs metallic source/drain, achieves good device characteristics. The normalized transconductance (Gmtox) compares very well with reported data for InGaAs n-MOSFETs formed on bulk InP substrates, and is significantly higher than reported data for In0.53Ga0.47As n-MOSFETs fabricated on Si substrates using a similar growth technique.

First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules

The first monolithic integration of Ge p-FETs and InAs n-FETs on silicon substrate using a sub-120 nm III-V buffer technology is reported. A common digital etch process was developed to precisely control the etching of InAs and Ge, enabling the realization of Ge p-FETs and InAs n-FETs with a body thickness Tbody of below 5 nm and channel lengths LCH smaller than 200 nm. Other process modules such as common gate stack and contact processes were also employed. By comparing with other reports that co-integrated Si1-xGex p-FETs and InxGa1-xAs n-FETs on Si or Ge substrates, the Ge p-FETs and InAs n-FETs in this work achieve the highest drive current ION.

P 2 S 5 /(NH 4 ) 2 S x -Based Sulfur Monolayer Doping for Source/Drain Extensions in n-Channel InGaAs FETs

Ultrashallow junctions that are abrupt and have low resistance are needed for the source/drain extensions (SDEs) of MOSFETs at future technology nodes. In addition, the use of 3-D devices, such as FinFETs or nanowire FETs, will require a doping process that is conformal. In this paper, we discuss P2S5/(NH4)2Sx-based doping for potential use in the formation of SDEs for n-channel InGaAs FETs. MOSFETs with source and drain formed using this doping technique are demonstrated. The effect of the dopant activation step on device performance is also studied.

Infrared spectroscopic ellipsometry study of sulfur-doped In0.53Ga0.47As ultra-shallow junctions

Sulfur mono-layer doped In0.53Ga0.47As films were investigated by infrared spectroscopic ellipsometry. The complex dielectric function of doped layers shows free carrier response which can be described by a single Drude oscillator. Electrical resistivities, carrier relaxation times, and active carrier depths are obtained for the shallow n-In0.53Ga0.47As films. Our results indicate that sub-10 nm sulfur-doped layers with active carrier concentration as high as 1.7 × 1019 cm−3 were achieved. Sheet resistances estimated from infrared spectroscopic ellipsometry are in good agreement with those obtained by electrical methods.

Self-aligned contact metallization for III–V channel Field-Effect Transistors

To achieve high drive current for III-V Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) in future technology nodes, potential performance bottlenecks such as high series resistance need to be addressed. In this paper, we review several self-aligned metallization technologies available for reducing the source/drain series resistance in planar and multiple-gate III-V MOSFETs. Novel approaches for forming self-aligned contacts in III-V MOSFETs in a manner similar to the salicidation process in Silicon Complementary Metal-Oxide-Semiconductor (CMOS) Technology will be discussed.

Growth temperature effects on graded In x Al 1−x As/GaAs buffer for metamorphic In 0.70 Ga 0.30 As/In 0.53 Al 0.47 As planar transistor on Ge-on-insulator(GeOI) substrate

This paper aims to investigate the effect of substrate temperature on molecular beam epitaxy-grown InxAl1-xAs graded buffer layer. Atomic force microscopy, cross-sectional transmission electron microscopy, and secondary ion mass spectroscopy are used for wafer characterization. TEM images are used to estimate the threading dislocation density in the wafer. To demonstrate the feasibility of this growth method for device integration, HEMT and HBT are also fabricated.

Growth of indium arsenide on silicon-based substrates using molecular beam epitaxy

Low defect InAs layers have been successfully grown on a GeOI substrate for the first time. The epitaxial structure grown allows the co-existence Si, Ge and InAs material on a single wafer. TEM and AFM results showed a low defect density and smooth InAs surface, respectively.

Plasma Doping of InGaAs at Elevated Substrate Temperature for Reduced Sheet Resistance and Defect Formation

Plasma doping (PLAD), a high-throughput ion implantation technique capable of achieving ultrashallow junctions and conformal doping of 3-D structures such as fin field-effect transistors, is investigated as an alternative to conventional beam-line ion implantation for InGaAs at advanced technology nodes. The PLAD at an elevated substrate temperature (ET-PLAD) is studied and reported for InGaAs for the first time. The ET-PLAD can give lower sheet resistance than room-temperature PLAD due to enhanced dopant incorporation. More crucially, an ET can help to prevent amorphization. After dopant activation anneal, residual corner defects are observed in small fins that are amorphized during plasma ion implantation, whereas fins that remain crystalline during plasma ion implantation are free of corner defects.

Ultra-thin-body In 0.7 Ga 0.3 As-on-nothing N-MOSFET with Pd-InGaAs source/drain contacts enabled by a new self-aligned cavity formation technology

We report the demonstration of an ultra-thin-body In0.7Ga0.3As-on-nothing N-MOSFET where a self-aligned cavity is formed right beneath the channel layer. Self-aligned Pd-InGaAs source/drain (S/D) contacts were integrated. The gate length LG of 130 nm is the smallest achieved with self-aligned contacts. With effective reduction of subsurface leakage current by the III-V-on-nothing device structure, DIBL of 248 mV/V and SS of 135 mV/decade were achieved.

Embedded Metal Source/Drain (eMSD) for series resistance reduction in In 0.53 Ga 0.47 As n-channel Ultra-Thin Body Field-Effect Transistor (UTB-FET)

We report a novel n-channel Ultra-Thin Body Field-Effect Transistor (UTB-FET) comprising an embedded Metal Source/Drain (eMSD) formed in a quasi-insulating InAlAs region. The InAlAs barrier layer reduces off-state leakage current IOFF significantly. The eMSD consists of conductive Ni-InGaAs and Ni-InAlAs layers, and has a low sheet resistance Rsh of ~20 Ω/square. This achieves a significant reduction in the parasitic S/D resistance Rsd, as compared with a conventional UTB-FET with thin S/D.