nan Ivana

Strained germanium-tin (GeSn) N-channel MOSFETs featuring low temperature N+/P junction formation and GeSnO2 interfacial layer

In this paper, we report the worlds first germanium-tin (GeSn) channel nMOSFETs. Highlights of process module advances are: low temperature (400 °C) process for forming high quality n+/p junction with high dopant activation and reduced dopant diffusion; interface engineering achieved with GeSnO2 interfacial layer (IL) between high-k gate dielectric and GeSn channel. A gate-last process was employed. The GeSn nMOSFET with GeSnO2 IL demonstrates a substantially improved SS in comparison with Ge control, and an ION/IOFF ratio of 104.

Crystal structure and epitaxial relationship of Ni4InGaAs2 films formed on InGaAs by annealing

The structural, compositional, and electrical properties of epitaxial Ni4InGaAs2 (denoted as Ni-InGaAs) film formed by annealing sputtered Ni film on InGaAs were investigated. It was found that Ni-InGaAs adopts a NiAs (B8) structure with lattice parameters of a = 0.396 ± 0.002 nm and c = 0.516 ± 0.002 nm, and exhibits an epitaxial relationship with InGaAs, with orientations given by Ni-InGaAs[1¯10]//InGaAs[001] and Ni-InGaAs[110]//InGaAs[110]. The epitaxial Ni4InGaAs2 film has bulk electrical resistivity of ∼102 μΩ·cm, which increases as the film thickness scales below 10 nm. The results of this work would be useful for the development of contact metallization for high mobility InGaAs metal-oxide-semiconductor field-effect transistors.

Tunneling field-effect transistor with Ge/In0.53Ga0.47As heterostructure as tunneling junction

High quality epitaxial germanium (Ge) was successfully grown on In0.53Ga0.47As substrate using a metal-organic chemical vapor deposition tool. The valence band offset ΔEV between the Ge layer and In0.53Ga0.47As determined by high-resolution x-ray photoelectron spectroscopy was found to be 0.5 ± 0.1 eV, suggesting the Ge/In0.53Ga0.47As heterojunction has a staggered band alignment at the interface. This makes the Ge/In0.53Ga0.47As heterojunction a promising tunneling junction for application in tunneling field-effect transistor (TFET). Lateral TFET with in situ doped p+ Ge-source In0.53Ga0.47As-channel using a gate-last process was demonstrated for the first time. The temperature dependence of the TFET transfer characteristics was investigated. The TFET with gate length (LG) of 8 μm exhibits an on-state tunneling current (ION) of 380 nA/μm at VGS = VDS = 2 V. The subthreshold swing (S) at the steepest part of the transfer characteristics of this device is ∼177 mV/decade. It was found that the off-state lea...

Photoelectron spectroscopy study of band alignment at interface between Ni-InGaAs and In0.53Ga0.47As

The work function of Ni-InGaAs and the band alignment between Ni-InGaAs and In0.53Ga0.47As were investigated using photoelectron spectroscopy. The vacuum work function of Ni-InGaAs is obtained to be ∼5.1 eV using ultraviolet photoelectron spectroscopy (UPS). In addition, it was observed that the Fermi level of Ni-InGaAs is aligned to near conduction band of In0.53Ga0.47As at interface. For Ni-InGaAs formed on p-type In0.53Ga0.47As, this gives a Schottky contact with a hole barrier height of 0.8 ± 0.1 eV. Ni-InGaAs would form an ohmic contact on n-type In0.53Ga0.47As.

N-channel InGaAs field-effect transistors formed on germanium-on-insulator substrates

InGaAs n-channel metal oxide semiconductor field-effect transistors (MOSFETs) were fabricated on germanium-on-insulator (GeOI) substrate for the first time. Integration of InGaAs on a GeOI substrate was achieved using a molecular beam epitaxy (MBE)-grown InAlAs graded buffer. The fabricated MOSFET, with a self-aligned Ni–InGaAs metallic source/drain, achieves good device characteristics. The normalized transconductance (Gmtox) compares very well with reported data for InGaAs n-MOSFETs formed on bulk InP substrates, and is significantly higher than reported data for In0.53Ga0.47As n-MOSFETs fabricated on Si substrates using a similar growth technique.

Source/Drain Engineering for In0.7Ga0.3As N-Channel Metal–Oxide–Semiconductor Field-Effect Transistors: Raised Source/Drain with In situ Doping for Series Resistance Reduction

In this paper, we report N-channel metal–oxide–semiconductor field-effect transistors (N-MOSFETs) featuring in situ doped raised In0.53Ga0.47As source/drain (S/D) regions. This is the first demonstration of such regrowth on an In0.7Ga0.3As channel. After SiON spacer formation, the raised In0.53Ga0.47As S/D structure was formed by selective epitaxy of In0.53Ga0.47As in the S/D regions by metal-organic chemical-vapor deposition (MOCVD). In situ silane SiH4 doping was also introduced to boost the N-type doping concentration in the S/D regions for series resistance RSD reduction. The raised S/D structure contributes to IDsat enhancement for the In0.7Ga0.3As N-MOSFETs.

Band alignment study of lattice-matched InAlP and Ge using x-ray photoelectron spectroscopy

Lattice-matched In0.49Ga0.51P was grown on a p-type Ge(100) substrate with a 10° off-cut towards the (111) by low temperature molecular beam epitaxy, and the band-alignment of In0.49Ga0.51P on Ge substrate was obtained by high resolution x-ray photoelectron spectroscopy. The valence band offset for the InGaP/Ge(100) interface was found to be 0.64 ± 0.12 eV, with a corresponding conduction band offset of 0.60 ± 0.12 eV. The InGaP/Ge interface is found to be of the type I band alignment.

In0.53Ga0.47As N-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Shallow Metallic Source and Drain Extensions and Offset N+ Doped Regions for Leakage Suppression

In this paper, we report the first demonstration of In0.53Ga0.47As n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs) with a shallow metallic source/drain extension (SDE) and offset n+ regions for leakage suppression. A SDE-last process flow was developed, i.e., the Ni–InGaAs metallic SDE was formed last, after formation of n+ doped source/drain (S/D) regions. The n+ S/D regions were offset from the gate edge with the use of sacrificial spacers. After spacer removal, self-aligned highly-abrupt Ni–InGaAs SDE was formed. Junction leakage between drain and body was effectively suppressed by ~40 times by the n+ S/D regions.

Pd-InGaAs as a new self-aligned contact material on InGaAs

Introduction. Self-alignment of source/drain (S/D) contacts to the transistor gate is important, as it brings the S/D contacts close to the channel and allows the achievement of low parasitic S/D series resistance RSD. Low RSD is needed for high-mobility and short-channel transistors where the channel resistance is low and external resistance is a significant proportion of the total resistance between source and drain. Fig. 1 illustrates the self-aligned S/D contact metallization process for InGaAs transistors. Recently, the first self-aligned Ni-InGaAs S/D contacts were demonstrated.1, 2 In this work, Pd-InGaAs is explored as a new self-aligned contact metallization technology.

Growth temperature effects on graded In x Al 1−x As/GaAs buffer for metamorphic In 0.70 Ga 0.30 As/In 0.53 Al 0.47 As planar transistor on Ge-on-insulator(GeOI) substrate

This paper aims to investigate the effect of substrate temperature on molecular beam epitaxy-grown InxAl1-xAs graded buffer layer. Atomic force microscopy, cross-sectional transmission electron microscopy, and secondary ion mass spectroscopy are used for wafer characterization. TEM images are used to estimate the threading dislocation density in the wafer. To demonstrate the feasibility of this growth method for device integration, HEMT and HBT are also fabricated.