Suman P. Sah

Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects

The Network-on-chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multihop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless NoC architecture where the multihop wire interconnects are replaced with high-bandwidth and single-hop long-range wireless shortcuts operating in the millimeter (mm)-wave frequency range. The proposed mm-wave wireless NoC (mWNoC) outperforms the corresponding conventional wireline counterpart in terms of achievable bandwidth and is significantly more energy efficient. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously further enhance the performance, and provide an energy-efficient solution for design of communication infrastructures for multicore chips.

Performance evaluation and design trade-offs for wireless network-on-chip architectures

Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multicore Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multihop links with high latency and power consumption. This limitation can be addressed by drawing inspiration from the evolution of natural complex networks, which offer great performance-cost trade-offs. Analogous with many natural complex systems, future multicore chips are expected to be hierarchical and heterogeneous in nature as well. In this article we undertake a detailed performance evaluation for hierarchical small-world NoC architectures where the long-range communications links are established through the millimeter-wave wireless communication channels. Through architecture-space exploration in conjunction with novel power-efficient on-chip wireless link design, we demonstrate that it is possible to improve performance of conventional NoC architectures significantly without incurring high area overhead.

A wideband body-enabled millimeter-wave transceiver for wireless Network-on-Chip

A highly energy-efficient on-chip communication network is crucial for the development of future multi-core chips. In this paper, a wideband millimeter-wave (mm-wave) transceiver was designed for the wireless Network-on-Chip (WiNoC) architecture. In order to reduce the power consumption of the transceiver, body-enabled circuit design techniques were implemented: Forward body-bias was used in the low-noise amplifier (LNA) and power amplifier (PA) circuits to lower the threshold voltages, reducing the supply voltage to 0.8 V. For up-and down-conversion mixers, power-hungry transconductance stages were eliminated by feeding the signals directly into the body terminals of the transistors. In addition, a novel feed-forward structure was designed to extend the bandwidth of the LNA at no cost in power consumption. Simulation results showed that the receiver has a double-sideband noise figure of less than 6 dB, and a peak gain of 20.5 dB, while the transmitter has an output P1dB of 0 dBm. The transceiver achieved an overall 3-dB bandwidth of 18 GHz. Compared with our previous design without body-enabled design techniques, the receiver power consumption was reduced by 20.3%.

A 1.2-pJ/bit 16-Gb/s 60-GHz OOK Transmitter in 65-nm CMOS for Wireless Network-On-Chip

This paper presents a high-efficiency 60-GHz on-off keying (OOK) transmitter (TX) designed for wireless network-on-chip applications. Aiming at an intra-chip communication distance of 20 mm, the TX consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator. For high efficiency, a common-source topology with a drain-to-gate neutralization technique is chosen for the DA. A detailed mathematical design methodology is derived for the neutralization technique. The bulk-driven OOK modulator employs a novel dual feedthrough cancellation technique, resulting in a 30-dB on-off ratio. Fabricated in a 65-nm bulk CMOS process, the TX consumes only 19 mW from a 1-V supply, and occupies an active area of 0.077 mm2. A maximum modulation data rate of 16 Gb/s with 0.75-dBm output power is demonstrated through measurements, which translates to a bit-energy efficiency of 1.2 pJ/bit.

Performance evaluation and receiver front-end design for on-chip millimeter-wave wireless interconnect

This paper illustrates the feasibility of designing a power-efficient millimeter-wave (mm-wave) transceiver for on-chip wireless communication networks. The performance of the on-chip wireless interconnect using mm-wave transceiver was evaluated through both theoretical analysis as well as system-level simulations in Simulink. To reduce the bit error rate degradation due to channel distortion, root-raised-cosine pulse shaping was performed. The simulation results were then used to define the design specifications of individual RF building blocks. Accordingly, a low-power receiver front-end, consisting of a three-stage wideband LNA, and a single-balanced down-conversion mixer, was also designed. The LNA was implemented using a feed-forward structure to extend the bandwidth at no cost in power consumption. The supply voltage of the mixer was reduced to 0.6 V by eliminating the transistor stack. Simulation results showed that the receiver has a 3-dB bandwidth of 19.2 GHz, a peak gain of 26.5 dB, a noise figure lower than 7.8 dB, and an input P1dB of −28 dBm, while consuming only 11.6 mW.

Design and Analysis of a Wideband 15–35-GHz Quadrature Phase Shifter With Inductive Loading

A Ku-, K-, and Ka-band phase shifter for beamforming applications is presented in this paper. An analysis showing the effect of loading conditions on quadrature phase accuracy in a simple poly-phase filter is carried out. Based on the analysis, a novel quadrature phase shifter (QPS) with inductive load is proposed. Sign-selection and vector addition is performed in two stages to lower supply voltage. The proposed phase shifter is fabricated in a 0.18- μm SiGe BiCMOS process and occupies an area of 520 μm×370 μm. The proposed QPS has a maximum phase error of 6.38° over 15-35 GHz while maintaining an amplitude imbalance less than 2 dB. When combined into a 4-bit phase shifter, the root mean square (rms) gain error is less than 2.2 dB and the rms phase error is less than 13° over 15-35 GHz. The phase shifter thus achieves a full 360° phase-shift range with 22.5 ° phase resolution. The total power consumption is 14 mA from a 1.8-V power supply. The phase shifter achieves an input P1dB of -6.25 dBm. The measured phase-shifting fractional bandwidth of 87% is the highest reported thus far in the literature for SiGe BiCMOS implementation.

Design Techniques for Load-Independent Direct Bulk-Coupled Low Power QVCO

Design techniques for a load-independent low-power low-phase-noise CMOS LC direct bulk-coupled quadrature voltage-controlled oscillator (DBC-QVCO) is presented in this paper. A capacitor tapping technique is used to lower the phase noise and achieve load-independent frequency of oscillation. Class-C operation is used to further reduce the phase noise and power consumption. Quadrature coupling is achieved using bulk coupling, leading to reduction in both power and area. The DBC-QVCO has been implemented in a standard 0.18-μm BiCMOS process and occupies an area of 0.3 mm2. The implemented DBC-QVCO achieves a measured phase noise of -114.2 dBc/Hz at 1-MHz offset from the 6.26-GHz carrier while consuming only 3.2 mW from a 1-V power supply. The DBC-QVCO achieves a figure of merit (FOM) of -185.1 dBc/Hz and an FOM with area of -190.3 dBc/Hz, which are among the best compared with recently published QVCOs operating in a similar frequency range.

A 12 GHz IF bandwidth low power 5–17 GHz V-band positive transformer-feedback down-conversion mixer

In this paper, a novel positive transformer feedback down-conversion mixer is proposed to boost conversion gain. An ultra-wideband RF input is achieved by feeding RF signal at the emitter of the switching pair. Switching devices are biased so as to minimize LO input power. Area is minimized by means of transformer coupling and shielded transmission line for RF routing. The proposed mixer is implemented in a 0.13 μm BiCMOS process and occupies an active area of only 190 μm × 140 μm. The mixer consumes only 2.2 mA from a 1.3 V supply. The mixer shows a 3 dB IF bandwidth of greater than 12 GHz with a peak conversion gain of -2.4 dB and IIP3 of 2.8 dBm at a LO power of just -13 dBm. The RF input return loss is better than -15 dB up to 67 GHz. The proposed mixer achieves best Figure-of-Merit with LO power (FOMPLO) and thus is most suited for wideband low power mm-wave receivers.

A 4.8 mW, 4.4 dB NF, wideband LNA using positively coupled transformer for V-band applications

In this paper, a V-band ultra-low power Low Noise Amplifier (LNA) with enhanced bandwidth (BW) is presented. A positively coupled cascode transformer (PCCT), formed using cascode inductors at the emitter of the cascode transistors, is used to couple the signal between the first and second stage. Using an optimum coupling factor of 0.23 for the PCCT, a bandwidth improvement of 15 % was seen during simulation. The prototype was implemented using 0.13 μm SiGe BiCMOS technology. Measurements show a peak gain of 13.5 dB, BW > 8 GHz, Noise Figure (NF) of 4.4 dB and an input 1-dB compression point (Pin,1dB) of -19 dBm. The LNA occupies a core area of only 0.05 mm2 and consumes 3.7 mA from a 1.3 V supply.

A low power 8 th sub-harmonic injection locked receiver for mm-Wave beamforming applications

This paper presents a single element V-band low power 8th sub-harmonic injection locked beamforming receiver. A significant savings in local oscillator (LO) routing power is achieved by using an 8th sub-harmonic injection locked oscillator (SILO) for frequency multiplication and phase-shifting. Power consumption of the LNA and mixer is lowered by means of transformer feedback techniques. The proposed receiver is implemented in a standard 0.13 μm BiCMOS process and occupies an active area of only 630 μm × 400 μm. The receiver consumes a minimum power of 11.4 mW and achieves a peak gain of 8.3 dB, IP1dB of -33.5 dBm, minimum NF of 7.7 dB and an IF bandwidth of larger than 11 GHz. A total phase-shift of 144° is measured. The proposed LO routing and phase-shifting scheme shows minimum power consumption among state-of-the-art receivers and is easily scalable to multiple elements.