Sumeet Kumar Gupta

A Three-Terminal Dual-Pillar STT-MRAM for High-Performance Robust Memory Applications

The design of a three-terminal self-aligned dual-pillar (DP) magnetic tunnel junction (MTJ) utilizing both current-induced spin-transfer torque (STT) and magnetic domain-wall motion effects is proposed for high-speed nonvolatile robust memory applications. The choice of a thin tunneling oxide (~0.9 nm) in a write-in port, spatially and electrically separated from a read-out port incorporating a thicker (~1.8 nm) oxide on an extended thin-film multilayer stack, significantly improves the overall cell stability and parametric process yield of a memory array. A dual-bit-line memory architecture incorporating a single-ended voltage-sensing scheme for fast data readout with just one access transistor per cell is also proposed for the first time. The technology-circuit cooptimization of the proposed single-transistor (1T) DP STT magnetic random access memory (MRAM) cell is carried out using effective mass-based transport simulations in nonequilibrium Greens function formalism and accurate micromagnetic simulations involving the Landau-Lifshitz-Gilbert-Slonczewski equation. The proposed DP STT-MRAM bit cell outperforms a state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell tunneling magnetoresistance, simplified memory array architecture with a single supply for read/write, and significantly lower probability of disturb and access failures under parametric process variations with a marginal increase in critical switching current.

KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells

The storage device in spin-transfer torque MRAM (STT-MRAM) is the magnetic tunneling junction (MTJ) and several models for the MTJ have been proposed. However, a simulation framework that captures device physics at the atomistic level when simulating STT-MRAM at the bit-cell level is lacking. We propose a simulation framework (KNACK) which models the MTJ at the atomistic level using the Non-Equilibrium Greens Function (NEGF) formalism and uses the NEGF model in conjunction with our STT-MRAM bit-cell circuit model for circuit-level simulations. Our simulation framework accepts I–V and C-V characteristics of the access device input either as lookup tables or as compact models. We show that with appropriate device and bit-cell parameters, our simulation framework has the ability to capture MTJ physics and simulate different genres of STT-MRAM bit-cells with results in agreement with experiments.

Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs

In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of current-voltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it is possible to achieve improvement in both read and write stability for the 6T SRAM bit cell, along with reduction in cell leakage at the cost of negligible increase in access time and area. We also propose a general circuit-aware device optimization methodology for SRAM design. We use this methodology to optimize the underlap in ADSE FinFETs. Compared to conventional FinFETs, we achieve 57% reduction in leakage, 11% improvement in read static-noise margin, and 6% improvement in write margin, with 7% increase in access time and cell area.

Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture

Spin-transfer torque magnetic RAM (STT MRAM) has emerged as a promising candidate for on-chip memory in future computing platforms. We present a cross-layer (device-circuit-architecture) approach to energy-efficient cache design using STT MRAM. At the device and circuit levels, we consider different genres of MTJs and bitcells, and evaluate their impact on the area, energy and performance of caches. In addition, we propose microarchitectural techniques viz. sequential cache read and partial cache line update, which exploit the non-volatility of STT MRAM to further improve energy efficiency of STT MRAM caches. A detailed comparison of STT MRAM caches with SRAM-based caches is also presented. Our results indicate that the proposed optimizations significantly enhance the efficiency of STT MRAM for designing lower level caches.

The design and hardware implementation of a low-power real-time seizure detection algorithm

Epilepsy affects more than 1% of the worlds population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 +/- 0.02% and 88.9 +/- 0.01% (mean +/- SE(alpha = 0.05)), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.

Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

We propose FinFETs with unequal source and drain doping concentrations [asymmetrically doped (AD) FinFETs] for low-power robust SRAMs. The effect of asymmetric source/drain doping on the device characteristics is extensively analyzed, and the key differences between conventional and AD FinFETs are clearly shown. We show that asymmetry in the device structure leads to unequal currents for positive and negative drain biases, which is exploited to achieve mitigation of read-write conflict in 6T SRAMs. The proposed device exhibits superior short-channel characteristics compared to a conventional FinFET due to reduced electric fields from the terminal that has a lower doping. This results in significantly lower cell leakage in AD-FinFET-based 6T SRAM. Compared to the conventional FinFET-based 6T SRAM, AD-FinFET SRAM shows 5.2%-8.3% improvement in read static noise margin (SNM), 4.1%-10.2% higher write margin, 4.1%-8.8% lower write time, 1.3%-3.5% higher hold SNM, and 2.1-2.5 lower cell leakage at the cost of 20%-23% higher access time. There is no area penalty associated with the proposed technique.

Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective

Ultralow-power dissipation can be achieved by operating digital circuits with scaled supply voltages, albeit with degradation in speed and increased susceptibility to parameter variations. However, operating digital logic and memory circuits in the subthreshold region (supply voltage less than the transistor threshold voltage) for ultralow-power operations requires device, circuit as well as architectural design optimizations, different from the conventional superthreshold design. This paper analyzes such optimizations from energy dissipation point of view and shows that it is feasible to achieve robust operation of ultralow-voltage systems. Operation with power supply as low as 60 mV is demonstrated. Techniques to reduce the impact of process variations on subthreshold circuits are also discussed. In addition, it is shown that subthreshold leakage current can be useful for other applications like thermal sensors.

Write-optimized reliable design of STT MRAM

Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is still a major challenge. As a result, the optimization of the memory for write is critical. In this work, we analyze asymmetric write currents in STT MRAMs considering process variations, and identify a potential for write power reduction. We propose circuit design techniques 1) bit-line voltage clamping using a pass transistor and 2) 2T-1R dual source-line bit-cell design, to balance out the asymmetric write currents and optimize the memory design from both write-power and reliability aspects. Our proposed techniques can be easily incorporated with previously proposed design techniques without affecting the bit-cell write-ability, read stability, and performance. We analyze the impact of our proposed techniques on write power and MTJ current density and show 30-68% average write power savings and 4-41% reduction in MTJ current density in STT MRAM.

Layout-aware optimization of STT MRAMs

We present a layout-aware optimization methodology for spin-transfer torque (STT) MRAMs, considering the dependence of cell area on the access transistor width (WFET), number of fingers in the access transistor and the metal pitch of bit- and source-lines. It is shown that for WFET less than a critical value (~7 times the minimum feature length), one-finger transistor yields minimum cell area. For large WFET, minimum cell area is achieved with a two-finger transistor. We also show that for a range of WFET, the cell area is limited by the metal pitch of bit- and source-lines. As a result, in the metal pitch limited (MPL) region, WFET can be increased with no change in the cell area. We analyze the impact of increase in WFET in the MPL region on the write margin and cell tunneling magneto-resistance (CTMR) of different genres of STT MRAMs. We consider conventional STT MRAM cells in the standard and reverse-connected configurations and STT MRAMs with tilted magnetic anisotropy for the analysis. By increasing WFET from the minimum to the maximum value in the MPL region (at iso-cell area) and reducing read voltage to achieve iso-read disturb margin, 2X improvement in write margin and 27% improvement in CTMR is achieved for the reverse-connected STT MRAM. Similar trends are observed for other STT MRAM cells.

Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors

We present a SPICE model for ferroelectric transistors (FEFETs) based on time-dependent Landau-Khalatnikov equation solved self-consistently with the transistor equations. The model also considers depolarization fields due to non-ideal contacts. We experimentally characterize FE films to calibrate our model, based on which we analyze the device and circuit implications of FEFETs. We discuss the dependence of the ON current and gate capacitance of FEFETs on the FE thickness and FE material parameters. A ring oscillator analysis shows delay reduction up to 97% at iso-energy for FEFETs compared with MOSFETs at VDD <; 0.4 V. FEFET-based SRAMs show 47%-68% larger read stability and 50%-57% lower access time, albeit with an increase in the write time.