Sumitha George

Nonvolatile memory design based on ferroelectric FETs

Ferroelectric FETs (FEFETs) offer intriguing possibilities for the design of low power nonvolatile memories by virtue of their three-terminal structure coupled with the ability of the ferroelectric (FE) material to retain its polarization in the absence of an electric field. Utilizing the distinct features of FEFETs, we propose a 2-transistor (2T) FEFET-based nonvolatile memory with separate read and write paths. With proper co-design at the device, cell and array levels, the proposed design achieves non-destructive read and lower write power at iso-write speed compared to standard FE-RAM. In addition, the FEFET-based memory exhibits high distinguishability with six orders of magnitude difference in the read currents corresponding to the two states. Comparative analysis based on experimentally calibrated models shows significant improvement of access energy-delay. For example, at a fixed write time of 550ps, the write voltage and energy are 58.5% and 67.7% lower than FERAM, respectively. These benefits are achieved with 2.4 times the area overhead. Further exploration of the proposed FEFET memory in energy harvesting nonvolatile processors shows an average improvement of 27% in forward progress over FERAM.

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors

Ferroelectric FETs (FEFETs) are emerging devices with potential for low power applications. The unique feature which makes these devices suitable for ultra-low voltage operation is the steep slope achieved by negative capacitance of the ferroelectric oxide based gate stack. This property is being actively explored to overcome the fundamental 60 mV/decade sub threshold swing limit associated with conventional MOSFETs. In this paper, we focus on the circuit implications of the steep slope behavior of the FEFETs. We analyze the characteristics of FEFETs to get insights into their performance, and show both higher ON current and higher gate capacitance compared to standard transistors. We design and simulate a ring oscillator and a Kogge Stone adder using FEFET devices and evaluate the impact of ferroelectric layer thickness on the performance. Our analysis shows that FEFET based circuits consume lower energy compared to CMOS circuits at VDD.

Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops

Nonvolatile computing has been proven to be effective in dealing with power supply outages for on-chip check-pointing in emerging energy-harvesting Internet-of-Things applications. It also plays an important role in power-gating to cut off leakage power for higher energy efficiency. However, existing on-chip state backup solutions for D flip–flop (DFF) have a bottleneck of significant energy and/or latency penalties which limit the overall energy efficiency and computing progress. Meanwhile, these solutions rely on external control that limits compatibility and increases system complexity. This paper proposes an approach to fundamentally advancing the nonvolatile computing paradigm by intrinsically nonvolatile area-efficient latches and flip–flops designs using negative capacitance FET. These designs consume fJ-level energy and ns-level intrinsic latency for a backup plus restore operation, e.g., 2.4 fJ in energy and 1.1 ns in time for one proposed nonvolatile DFF with a supply power of 0.80 V.

Ferroelectric Transistor based Non-Volatile Flip-Flop

We present a non-volatile flip-flop with a feature to back-up the state in a ferroelectric transistor (FEFET) during power failure or supply gating. The data is stored in the form of polarization of the ferroelectric (FE) layer in the gate stack of the FEFET. The proposed flip-flop utilizes the non-volatility of the three-terminal FEFET to optimize the data backup and restore operations. We perform an extensive device-circuit analysis to provide insights into the design of the proposed flip-flop. We discuss the optimization of the FE thickness in the gate stack of the FEFET to introduce suitable non-volatility and present the implications at the circuit level. Our analysis shows that by virtue of the three terminal structure of the FEFET and the order of magnitude difference in the current for the two polarization states, the design of the backup/restore module is considerably simplified. Compared to a FE capacitor based non-volatile flip-flop, the proposed flip-flop achieves 40%--50% smaller backup delay, 27%--40% lower backup energy, comparable restore delay and up to an order of magnitude lower restore energy. While the FE capacitor based design leads to 76% area penalty compared to a conventional (volatile) flip-flop, the proposed design incurs only 35% area overhead.

Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures

The Internet-of-Things (IoT) has excited low-power design from device, circuits, to architectures levels. This paper talks about how recent emerging beyond-CMOS devices, such as tunnel field effect transistor (TFET), negative capacitance FET (NCFET), and phase transition devices (PTD), could extend the low-power design space to enable IoT applications with beyond-CMOS features.

Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore

Nonvolatile SRAM (nvSRAM) has emerged as a promising approach to reducing the standby energy consumption by storing the state into an in situ nonvolatile memory element and shutting down the power supply. Existing nvSRAM solutions based on a nonvolatile backup in magnetic tunnel junction and ReRAM, however, are costly in backup and restore energy due to static current. This cost results in a long break-even time (BET) when compared with a lowered voltage standby volatile SRAM. This brief proposes an nvSRAM based on ferroelectric FETs (FeFETs) that are capable of fully avoiding such static current. A simple differential backup and restore circuitry is proposed, achieving sub-fJ/cell total energy per backup and restore operation at the 10-nm node. This leads to hundreds of times BET improvement over existing ReRAM nvSRAM solutions. This nvSRAM also indicates the future FeFET design trends for such memory-logic synergy.

Emerging Steep-Slope Devices and Circuits: Opportunities and Challenges

While continuing the CMOS scaling-down becomes unprecedentedly more challenging than before, intensive exploration on beyond-CMOS nanodevice technologies is an appealing approach to further continue the power scaling-down. This chapter reviews some promising beyond-CMOS emerging transistor technologies, including Tunnel FETs, Ferroelectric FETs, and Hyper-FETs. Circuit design techniques based on these emerging devices are also reviewed to provide insights for future energy-efficient analog and digital signal processing. In addition to the opportunities, this chapter also discusses the challenges of emerging devices in circuit and systems.

Sensing in Ferroelectric Memories and Flip-Flops

Ferroelectric (FE) materials, by virtue of their polarization retention in the absence of the electric field, offer a unique method to introduce non-volatility in memories and logic. The exploration of FE materials in context of their application in compute and storage has been carried out in two forms: (1) as capacitors, in which the FE material is sandwiched between two metal layers and (2) in ferroelectric transistors (FEFETs), in which, FE is integrated into the gate stack of FETs. Both the devices have been explored to design non-volatile memories and flip-flops. The commonality between the two technologies is that they use remnant polarization in the FE to define the binary logic states. However, the sensing as well as the switching of the polarization requires considerably different techniques for FE capacitors and transistors. Moreover, the requirements of the application (memory, flip-flop, etc.) also dictate the methodology for reading or writing the logic state. This chapter discusses the device–circuit aspects of FE capacitors and FEFETs in the context of non-volatile memory and logic design, with a focus on the sensing techniques. We present a comparative description of the two technologies, highlighting the pros and cons of each and how different device structures yield significantly different sensing strategy.

Harnessing ferroelectrics for non-volatile memories and logic

Ferroelectrics (FE) have been the materials of interest for non-volatile memories for many decades due to their hysteretic charge-voltage behavior. However, recently, the possibilities of integrating an FE in the gate stack of a transistor (forming a ferroelectric transistor or FEFET) have opened new avenues for computation and storage. The FEFETs not only enhance the design of non-volatile memories, but also lead to the unique possibilities of introducing non-volatility in close proximity with the compute elements. In this paper, we comparatively analyze several device and circuit aspects of FEFETs and FE capacitors from the perspective of designing non-volatile memory and logic. We discuss the effect of integrating an FE in a transistor structure on the remnant polarization and coercive voltage and show the importance of FE thickness optimization to design a non-volatile transistor. We also present circuit design possibilities with non-volatile FEFETs. First, the design of memories with separate read-write paths is discussed. We show that compared to FE capacitor based memories, FEFETs achieve enormous distinguishability and near read disturb free operation albeit with 2.5× higher cell area and 3.6× higher write energy at iso-write time. Second, we describe the opportunities that non-volatility combined with the three terminal architecture of FEFETs presents in the design of low power non-volatile flip-flops. We show that compared to FE capacitor based flip-flops, FEFET based design yields upto 50% lower energy and up to 40% lower delay for data back-up, along with 30% lower area.