Ahmedullah Aziz

Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors

We present a SPICE model for ferroelectric transistors (FEFETs) based on time-dependent Landau-Khalatnikov equation solved self-consistently with the transistor equations. The model also considers depolarization fields due to non-ideal contacts. We experimentally characterize FE films to calibrate our model, based on which we analyze the device and circuit implications of FEFETs. We discuss the dependence of the ON current and gate capacitance of FEFETs on the FE thickness and FE material parameters. A ring oscillator analysis shows delay reduction up to 97% at iso-energy for FEFETs compared with MOSFETs at VDD <; 0.4 V. FEFET-based SRAMs show 47%-68% larger read stability and 50%-57% lower access time, albeit with an increase in the write time.

Nonvolatile memory design based on ferroelectric FETs

Ferroelectric FETs (FEFETs) offer intriguing possibilities for the design of low power nonvolatile memories by virtue of their three-terminal structure coupled with the ability of the ferroelectric (FE) material to retain its polarization in the absence of an electric field. Utilizing the distinct features of FEFETs, we propose a 2-transistor (2T) FEFET-based nonvolatile memory with separate read and write paths. With proper co-design at the device, cell and array levels, the proposed design achieves non-destructive read and lower write power at iso-write speed compared to standard FE-RAM. In addition, the FEFET-based memory exhibits high distinguishability with six orders of magnitude difference in the read currents corresponding to the two states. Comparative analysis based on experimentally calibrated models shows significant improvement of access energy-delay. For example, at a fixed write time of 550ps, the write voltage and energy are 58.5% and 67.7% lower than FERAM, respectively. These benefits are achieved with 2.4 times the area overhead. Further exploration of the proposed FEFET memory in energy harvesting nonvolatile processors shows an average improvement of 27% in forward progress over FERAM.

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors

Ferroelectric FETs (FEFETs) are emerging devices with potential for low power applications. The unique feature which makes these devices suitable for ultra-low voltage operation is the steep slope achieved by negative capacitance of the ferroelectric oxide based gate stack. This property is being actively explored to overcome the fundamental 60 mV/decade sub threshold swing limit associated with conventional MOSFETs. In this paper, we focus on the circuit implications of the steep slope behavior of the FEFETs. We analyze the characteristics of FEFETs to get insights into their performance, and show both higher ON current and higher gate capacitance compared to standard transistors. We design and simulate a ring oscillator and a Kogge Stone adder using FEFET devices and evaluate the impact of ferroelectric layer thickness on the performance. Our analysis shows that FEFET based circuits consume lower energy compared to CMOS circuits at VDD.

Phase-Transition-FET exhibiting steep switching slope of 8mV/decade and 36% enhanced ON current

Vanadium dioxide (VO2), which exhibits electrically induced abrupt insulator-to-metal phase transition (IMT), is monolithically integrated with Silicon MOSFET to demonstrate a steep-slope (sub-kT/q) Phase-Transition FET (Phase-FET). The Phase-FET exhibits switching-slope (SS) of 8mV/decade leading to 36% increase in ON current (ION) over baseline MOSFET. We analyze the electrical characteristics of several threshold-switching materials with enhanced resistivity ratios (>105) beyond VO2 and harness them to enhance the performance of 14nm node FinFETs. Our analysis shows that up to 2.9× increase in ION, and 1.86× reduction in energy at (iso-delay) for an 11 stage ring oscillator (RO) is achievable with Phase FETs using Cu-doped HfO2 threshold switches.

Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops

Nonvolatile computing has been proven to be effective in dealing with power supply outages for on-chip check-pointing in emerging energy-harvesting Internet-of-Things applications. It also plays an important role in power-gating to cut off leakage power for higher energy efficiency. However, existing on-chip state backup solutions for D flip–flop (DFF) have a bottleneck of significant energy and/or latency penalties which limit the overall energy efficiency and computing progress. Meanwhile, these solutions rely on external control that limits compatibility and increases system complexity. This paper proposes an approach to fundamentally advancing the nonvolatile computing paradigm by intrinsically nonvolatile area-efficient latches and flip–flops designs using negative capacitance FET. These designs consume fJ-level energy and ns-level intrinsic latency for a backup plus restore operation, e.g., 2.4 fJ in energy and 1.1 ns in time for one proposed nonvolatile DFF with a supply power of 0.80 V.

Ferroelectric Transistor based Non-Volatile Flip-Flop

We present a non-volatile flip-flop with a feature to back-up the state in a ferroelectric transistor (FEFET) during power failure or supply gating. The data is stored in the form of polarization of the ferroelectric (FE) layer in the gate stack of the FEFET. The proposed flip-flop utilizes the non-volatility of the three-terminal FEFET to optimize the data backup and restore operations. We perform an extensive device-circuit analysis to provide insights into the design of the proposed flip-flop. We discuss the optimization of the FE thickness in the gate stack of the FEFET to introduce suitable non-volatility and present the implications at the circuit level. Our analysis shows that by virtue of the three terminal structure of the FEFET and the order of magnitude difference in the current for the two polarization states, the design of the backup/restore module is considerably simplified. Compared to a FE capacitor based non-volatile flip-flop, the proposed flip-flop achieves 40%--50% smaller backup delay, 27%--40% lower backup energy, comparable restore delay and up to an order of magnitude lower restore energy. While the FE capacitor based design leads to 76% area penalty compared to a conventional (volatile) flip-flop, the proposed design incurs only 35% area overhead.

Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits

Numerous research efforts are targeting new devices that could continue performance scaling trends associated with Moores Law and/or accomplish computational tasks with less energy. One such device is the ferroelectric FET (FeFET), which offers the potential to be scaled beyond the end of the silicon roadmap as predicted by ITRS. Furthermore, the Ids vs. Vgs characteristics of FeFETs may allow a device to function as both a switch and a non-volatile storage element. We exploit this FeFET property to enable fine-grained logic-in-memory (LiM). We consider three different circuit design styles for FeFET-based LiM: complementary (differential), dynamic current mode, and dynamic logic. Our designs are compared with existing approaches for LiM (i.e., based on magnetic tunnel junctions (MTJs), CMOS, etc.) that afford the same circuit-level functionality. Assuming similar feature sizes, non-volatile FeFET-based LiM circuits are more efficient than functional equivalents based on MTJs when considering metrics such as propagation delay (2.9×, 6.8×) and dyanmic power (3.7×, 2.3×) (for 45 nm, 22 nm technology respectively). Compared to CMOS functional equivalents, FeFET designs still exhibit modest improvements in the aforementioned metrics while also offering non-volatility and reduced device count.

Ag/HfO 2 based threshold switch with extreme non-linearity for unipolar cross-point memory and steep-slope phase-FETs

We demonstrate a novel Ag/HfO2 based threshold switch (TS) with a selectivity∼107, a high ON-state current (Ion) of 100 μA, and ∼10pA leakage current. The thresholding characteristics of the TS result from electrically triggered spontaneous formation and rupture of an Ag filament which acts an interstitial dopant in the HfO2 insulating matrix. Further, we harness the extreme non-linearity of the TS in (1) Selectors for Phase Change Memory (PCM) based cross-point memory. We show through array level simulations of a 1024kb memory, a read margin of 28% and write margin of 32% for a leakage power of <25μW (V/3 scheme); (2) A steep-slope sub-kT/q Phase-FET, experimentally demonstrating a switching-slope (SS) of 3mV/decade (over 5 orders of Ids), and >10x Ion improvement over the conventional FET (at iso-Ioff) at T=90C (50x at T=25C); making this a promising TS for both emerging memory, and steep-slope transistor applications.

Analysis of Functional Oxide based Selectors for Cross-Point Memories

We present an extensive analysis of functional-oxide based selector devices for cross-point memories from the perspectives of materials through arrays. We describe the design constraints required for proper functionality of a cross-point array and translate these constraints to figures of merit for the selector materials. The proposed figures of merit, related to the resistivities of the functional oxide in the metallic and insulating states and the critical current densities for insulator-metal transitions, determine whether or not a functional oxide is suitable to be employed as a selector for a memory technology. Our analysis shows the importance of co-optimizing the selector length with the read/write voltages and establishes the range of these parameters for proper functionality. We also perform an extensive material space analysis for the selector, relating the selector properties to the achievable array metrics. For instance, we show that optimized memory array with single crystal VO2 based selector and spin-memory element achieves ~ 25μA sense margin with ~ 30% read disturb margin and 40ns write time. The leakage in the half-accessed cell can be as low as 15μW. The design principles established in this work will provide guidelines for future exploration of functional oxides for selector applications as well as for the optimization of cross-point arrays.

COAST: Correlated material assisted STT MRAMs for optimized read operation

We present a novel technique for optimizing the read operation of spin-transfer torque (STT) MRAMs by employing a correlated material in conjunction with a magnetic tunnel junction (MTJ). The design of the proposed memory cell is based on exploiting the orders-of-magnitude difference in the resistance of the two phases of the correlated material (CM) and triggering operation-driven phase transitions in the CM by judiciously co-optimizing devices and the memory cell. During read, the CM operates in the metallic and insulating phases when the MTJ is in the low resistance and high resistance states, respectively. This leads to superior distinguishability, read efficiency and stability. During write, the CM operates in the metallic phase, which minimizes the impact of the CM resistance on the write speed. Our analysis shows that CM amplifies the cell tunneling magneto-resistance from 107% (for the standard STT MRAM) to 1878% (for the proposed cell) leading to 68% higher sense margin. In addition, 45% enhancement in the read disturb margin and 36% reduction in the cell read power is achieved. At the same time, the write asymmetry associated with different state transitions is mildly mitigated, leading to 9% reduction in the write power. This comes at a negligible cost of 4% larger write time. We also discuss the layout implications of our technique and propose the sharing of the CM amongst multiple cells. As a result of the sharing, the proposed technique incurs no area penalty.