Sumeet Saurav

Comprehensive Review and Comparative Analysis of Hardware Architectures for Sobel Edge Detector

This paper presents a comprehensive review and a comparative study of various hardware/FPGA implementations of Sobel edge detector and explored different architectures for Sobel gradient computation unit in order to show the various trade-offs involved in choosing one over another. The different architectures using pipelining and/or parallelism (key methodologies for improving the performance/frame rates) are explored for gradient computation unit in Sobel edge detector. How the different architectures affected performance (in terms of video frame rate and image size) and area (in terms of FPGA resources usages) has been demonstrated. By exploiting the trade-offs between video frame rate, image size, and FPGA resources a designer should be able to find an optimal architecture for a given application.

Hardware accelerator for real-time image resizing

An accurate, hardware efficient and fast image rescaling unit is a crucial part of any real-time image processing system. Although there are a number of image scaling algorithms existing in the literature but Bicubic and Bilinear interpolation algorithms are most widely used. In the recent years, numerous algorithms have been proposed that aim to bridge the gap between these two standard algorithms, by attempting to provide high image quality of the former while maintaining the computational simplicity of the latter. This paper proposes a novel image resizing algorithm which uses a four-part piecewise linear function that closely mimics the behavior of the bicubic kernel, and thus provides high quality resized images comparable to Bicubic interpolation while having a much lower computational cost. An optimized architecture is proposed to implement this algorithm which features a high re-use of hardware units for coefficient generation so that the hardware cost is comparable to that of bilinear interpolation. The architecture and algorithm have been designed in tandem so as to meet the real-time requirements of applications such as automated video surveillance, requiring minimal hardware use without compromising on image quality.

Analyzing impact of image scaling algorithms on viola-jones face detection framework

In todays world of automation, real time face detection with high performance is becoming necessary for a wide number of computer vision and image processing applications. Existing software based system for face detection uses the state of the art Viola and Jones face detection framework. This detector makes use of image scaling approach to detect faces of different dimensions and thus, performance of image scalar plays an important role in enhancing the accuracy of this detector. A low quality image scaling algorithm results in loss of features which directly affects the performance of the detector. Therefore, in this paper we have analyzed the effect of different image scaling algorithms existing in literature on the performance of the Viola and Jones face detection framework and have tried to find out the optimal algorithm significant in performance. The algorithms which will be analyzed are: Nearest Neighbor, Bilinear, Bicubic, Extended Linear and Piece-wise Extended Linear. All these algorithms have been integrated with the Viola and Jones face detection code available with OpenCV library and has been tested with different well know databases containing frontal faces.

Hardware Accelerator for Facial Expression Classification Using Linear SVM

In this paper, we present hardware accelerator for Facial Expression Classification using One-Versus-All (OVA) linear Support Vector Machine (SVM) classifier. The motivation behind this work is to perform real-time classification of facial expressions into three different classes: neutral, happy and pain, which could be used in an embedded system to facilitate automatic patient monitoring in ICUs of hospitals without any personal assistance. Pipelining and parallelism (inherent qualities of FPGAs) have been utilized in our architecture to achieve optimal performance. For achieving high accuracy, the architecture has been designed using IEEE-754 single precision floating-point data format. We performed the SVM training offline and used the trained parameters to implement its testing part on Field Programmable Gate Array (FPGA). Synthesis result shows that the designed architecture is operating at a maximum clock frequency of 200 MHz. Classification accuracy of 97.87% has been achieved on simulating the design with different test images. Thus, the designed architecture of the OVA linear SVM shows good performance in terms of both speed and accuracy facilitating real-time classification of the facial expressions.

Analyzing hardware constraints of Gabor filtering operation for Facial Expression Recognition System

This paper presents hardware constraints analysis of Gabor filtering operation for its hardware implementation in a real time Facial Expression Recognition System (FERS). Gabor filter is the most common feature extractor employed for the realization of such system. Feature extraction using Gabor filter is efficient and has better discrimination capability. In this work, we have employed software-based approach to find the optimum filter and facial image size. These two factors employed in the Gabor filtering process directly affect the hardware resource utilization and hence we have considered these two factors for our analysis. We have used two versions of Gabor filter for feature extraction, one using the original Gabor filtering approach and the other its modified version using Image Pyramid based approach. Support Vector Machine (SVM) classifier has been used for analyzing the performance of the extracted feature.

VLSI architecture of Pairwise Linear SVM for facial expression recognition

In this paper, we present VLSI architecture of Pairwise Linear Support Vector Machine (SVM) classifier for multi-classification on FPGA. The objective of this work is to facilitate real time classification of the facial expressions into three categories: neutral, happy and pain, which could be used in a typical patient monitoring system. Thus, the challenge here is to achieve good performance without compromising the accuracy of the classifier. In order to achieve good performance pipelining and parallelism (key methodologies for improving the performance/frame rates) have been utilized in our architectures. We have used pairwise SVM classifier because of its greater accuracy and architectural simplicity. The architectures has been designed using fixed-point data format. Training phase of the SVM is performed offline, and the extracted parameters have been used to implement testing phase of the SVM on the hardware. According to simulation results, maximum frequency of 241.55 MHz, and classification accuracy of 97.87% has been achieved, which shows a good performance of our proposed architecture.

FPGA-based real-time object tracker using modified particle filtering and SAD computation

Tracking of objects of interest is of great significance for video based automated surveillance systems. This research presents the design and implementation of Xilinx ML510 (Virtex-5 FXT) FPGA platform based vision system for real-time object tracking in a video sequence. Modified particle filtering and sum of absolute differences (SAD) based scheme is used for object tracking. The proposed complete system is designed to meet the real-time requirements of video surveillance applications. The implemented system can robustly track the objects present in a video stream in real-time for standard PAL size color video.

Automatic real-time extraction of focused regions in a live video stream using edge width information

This paper presents the design of a dedicated VLSI architecture for focused region extraction in a video sequence and its implementation on Virtex-5 (ML510) FPGA platform. Edge width based scheme is used for focused region extraction. The proposed architecture is designed to meet the real-time requirements of video surveillance applications. It is capable of robustly extracting the focused regions in a live video stream in real-time for standard PAL size color video.

FPGA-Based Smart Camera System for Real-Time Automated Video Surveillance.

Automated video surveillance is a rapidly evolving area and has been gaining importance in the research community in recent years due to its capabilities of performing more efficient and effective surveillance by employing smart cameras. In this article, we present the design and implementation of an FPGA-based smart camera system for automated video surveillance. The complete system is prototyped on Xilinx ML510 FPGA platform and meets the real-time requirements of video surveillance applications while aiming at FPGA resource reduction. The implemented smart camera system is capable of automatically performing real-time motion detection, real-time video history generation, real-time focused region extraction, real-time filtering of frames of interest, and real-time object tracking of identified target with automatic purposive camera movement. The system is designed to work in real-time for live color video streams of standard PAL (720 × 576) resolution, which is the most commonly used video resolution for current generation surveillance systems. The implemented smart camera system is also capable of processing HD resolution video streams in real-time.

High Frame Rate Real-Time Scene Change Detection System

Scene change detection, one of the fundamental and most important problem of computer vision, plays a very important role in the realization of a complete industrial vision system as well as automated video surveillance system - for automatic scene analysis, monitoring, and generation of alerts based on relevant changes in a video stream. Therefore, in addition to being accurate and robust, a successful scene change detection system must also be of very high frame rate in order to detect scene changes which goes off within a glimpse of the eye and often goes unnoticeable by the conventional frame rate cameras. Keeping the high frame rate processing as main focus, a very high frame rate real-time scene change detection system is developed by leveraging VLSI design to achieve high performance. This is accomplished by proposing, designing, and implementing an area-efficient scene change detection VLSI architecture on FPGA-based IDP Express platform. The developed prototype of complete real-time scene change detection system is capable of processing 2000 frames per second for 512 × 512 video resolution and is tested for live incoming video streams from high speed camera. The proposed and implemented system architecture is adaptable and scalable for different video resolutions and frame rates.