Sung-Hyung Park
Chungnam National University
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Featured researches published by Sung-Hyung Park.
Continental Shelf Research | 1999
Sung-Hyung Park; D.-G. Yoo; Kyu-Chul Lee; Hoonsoo Lee
Recent muds accumulating in the southeastern Korea Sea (Korea Strait) are mostly derived from the Nakdong River discharge and can be divided into the Proximal Mud Deposits (PMD) and the Distal Mud Deposits (DMD). The PMD show a relatively well- or weakly stratified subbottom on high-resolution seismic profiles (3.5 kHz and Uniboom), whereas the DMD are acoustically characterized by a transparent subbottom and the extensive occurrence (about 900 km2 in area) of acoustic turbidity in shallow sediments. 210Pb excess activity profiles of sediment cores yield apparent sediment accumulation rates of 1.8–4.4 mm/yr. On the basis of an average sediment accumulation rate, suspended-sediment budget in the PMD and the DMD was calculated, which provides important information about distribution patterns and transport directions. The PMD are a direct sink of about 35% (1.65×106 t/yr) of total fine-grained sediments released from the Nakdong River. The remaining riverine sediments are transported farther to northeastward in response to the strong coastal front between the coastal circulation and the offshore Tsushima Current. An annual sink of sediments in the DMD is estimated to be 2.9×106 t/yr that are approximately 63% of the annual discharge of suspended sediments by the Nakdong River. Additionally, average contents of organic carbon and nitrogen in the DMD are about two times of those in the PMD, reflecting high biological productivity associated with coastal upwelling process in this area. The coastal upwelling process is also supported by C/N ratio, sea-surface temperatures and chlorophyll pigment concentrations.
Geosciences Journal | 1997
Sung Kwun Chough; S.H. Lee; Jun-su Kim; Sung-Hyung Park; D. G. Yoo; H. S. Han; S. H. Yoon; S. B. Oh; Y. B. Kim; G. G. Back
High-resolution (Chirp, 2–7 kHz) reflection profiles in the Ulleung Basin (35–37°N) made it possible to classify the uppermost (ca. 50–70 m thick) sedimentary sequence into eleven discrete echo types. They are either (1) distinct (Echo Types IA, IB, IC, ID, IE, and IF), (2) indistinct (Echo Types IIA, IIB, and IIC), (3) hyperbolic (Echo Type III), or (4) combined (Echo Type IV).Echo Type IA is characterized by a sharp, continuous bottom echo with no subbottom reflectors (interpreted as deposits of sand and gravel). Echo Type IB shows a sharp bottom echo with discrete, continuous subbottom reflectors and either flat or undulatory surface topography (most likely turbidites). Echo Type IC is characterized by a distinct, smooth bottom echo (inclined) with parallel subbottom reflectors (interpreted as deposits of bottom currents or hemipelagic settiing). Echo Type ID is represented by a sharp bottom echo with diffuse, discontinuous, subparallel subbottom reflectors (probably deposits of sand and gravel). Echo Type IE is characterized by a sharp bottom reflector on the channelized subsurface topography with either inclined, channelized, or transparent internal reflectors (interpreted as buried fluvial channels). Echo Type IF shows a distinct bottom reflector with prolonged subbottom echoes and irregular surface topography (basement highs). Echo Type IIA is represented by a semi-prolonged bottom echo with intermittent subbottom reflectors and smooth or undulatory surface topography (most likely turbidites). Echo Type IIB shows a prolonged bottom echo with no subbottom reflectors (interpreted as turbidites). Echo Type IIC is characterized by laterally wedged, transparent subbottom echoes with variable bottom echoes (interpreted as debrites). Echo Type III shows regular, over-lapping hyperbolae with slightly varying vertex elevations (interpreted as debrites). Echo Type IV is represented by irregular blocky, lumpy, or hyperbolic masses, with various amount of internal deformation, bounded upslope by scars (slide/slump deposits and mass-failure scars).The shelfal areas are dominated by distinct echoes: the southern shelf by Echo Types IA, ID, and IE; the eastern shelf by Echo Type ID; the western shelf by Echo Type IF. The upper-to-middle slope region is generally characterized by Echo Type IV; the western slope by Echo Type IC. The lower slope is commonly occupied by Echo Types III and IIC (southern margin) and Echo Type IIC (western and eastern margins). The basin floor is generally dominated by Echo Types IIB, IIA, and IB. Echo characters show a zonal distribution: Echo Type IV (slump and scars) on the upper slope, Echo Types IIC and III (debrites) on the middle to lower slope and the base-of-slope, and Echo Types IIB, IIA, and IB (turbidites) on the basin floor. This distribution generally suggests that sediments were supplied from a linear source with large-scale flow transformations of sediment gravity flows.
international electron devices meeting | 2007
Tom Joy; Sung Gyu Pyo; Sung-Hyung Park; Chang-Hoon Choi; Chintamani Palsule; Hyungjun Han; Chen Feng; Sangjoo Lee; Jeff McKee; Parker Altice; Chris Sungkwon Hong; Christian Boemler; Jerry Hynecek; Michael Louie; Juil Lee; Dae-Byung Kim; Homayoon Haddad; Bedabrata Pain
A back-illuminated 2 megapixel CMOS sensor utilizing mature wafer manufacturing operations is described. Sensitivity, dark current and other key pixel performance measures are compared against an equivalent conventional sensor. Aspects of the process integration that make the technology manufacturable are described. Simulations that predict the performance of a full color sensor are discussed.
international electron devices meeting | 2005
Hee-Hwan Ji; Yong-Goo Kim; In-Shik Han; Kyung Min Kim; Jin-Suk Wang; Hi-Deok Lee; Won-Joon Ho; Sung-Hyung Park; Heui-Seung Lee; Young-Seok Kang; Dae-Byung Kim; Chang-Young Lee; Ihl-Hyun Cho; Sang-Young Kim; Sung-Bo Hwang; Jeong-Gun Lee; Jin Won Park
For the first time, on-chip charge pumping method is proposed to characterize ultra thin gate oxide for nano-scale CMOSFETs. Designed on-chip charge pumping system can supply 30-500MHz square-type pulse waves to DUT transistor and measured charge pumping current showed no gate tunneling current dependency which can be easily monitored in very thin gate oxide. In addition to the measurement of interface states by fixed-amplitude method, the distribution of interface states in channel region can be easily extracted by fixed-base method using this system. The proposed method is also successfully applied to analyze hot-carrier stress-induced threshold voltage (Vt)-degradation and to evaluate plasma process induced damage in terms of interface trap density
IEEE Transactions on Nanotechnology | 2007
Jang-Gn Yun; Soon-Young Oh; Bin-Feng Huang; Yong-Jin Kim; Hee-Hwan Ji; Yong-Goo Kim; Sung-Hyung Park; Heui-Seung Lee; Dae-Byung Kim; Ui-Sik Kim; Han-Seob Cha; Sang-Bum Hu; Jeong-Gun Lee; Hi-Deok Lee
In this paper, novel Ni germanosilicide technology using NiPt alloy and Co overlayer has been proposed. Using the Co overlayer after NiPt deposition on Si1-xGex, the formation temperature of low resistive Ni germanosilicide is lowered with high thermal stability. The thermal stability of Ni germanosilicide with different Ge fraction in is also characterized. The sheet resistance degrades as increasing the Ge fraction (x) in Si1-xGex when NiPt/TiN is used. However, using the Co overlayer, the sheet resistance property among Ni germanosilicide formed with different Ge fraction is improved greatly compared with those of NiPt/TiN case (without Co overlayer). Therefore, low-temperature formation of highly thermal robust Ni germanosilicide can be achieved through the NiPt/Co/TiN tri-layer.
Japanese Journal of Applied Physics | 2008
In-Shik Han; Hee-Hwan Ji; Tae-Gyu Goo; Ook-Sang Yoo; Won-Ho Choi; Min-Ki Na; Yong-Goo Kim; Sung-Hyung Park; Heui-Seung Lee; Young-Seok Kang; Dae-Byung Kim; Hi-Deok Lee
In this paper, we investigated the device performance and negative bias temperature instability (NBTI) degradation for thermally nitrided oxide (TNO) and plasma nitrided oxide (PNO) in nanoscale p-channel metal oxide semiconductor field effect transistor (PMOSFET). PNOs show the improvement of dielectric performance compared to TNO with no change of the device performance. PNOs also show the improvement of NBTI immunity than TNO at low temperature stress, whereas NBTI immunity of PNO with high N concentration can be worse than TNO at high temperature stress. Recovery effect of NBTI degradation of PNO is lower than that of TNO and it is increased as the N concentration is increased in PNO because the dissociated Si dangling bonds and generated positive oxide charges are repassivated and neutralized, respectively. Moreover, complete recovery of ΔVth is dominated by neutralization of positive oxide charges. Therefore, N contents at polycrystalline Si/SiO2 interface as well as N contents at Si/SiO2 interface can affect significantly on NBTI degradation and recovery effect.
international symposium on plasma process induced damage | 2001
Sung-Hyung Park; Hi-Deok Lee; Key-Min Lee; Myoung-Jun Jang; Joo Hyoung Lee; Geun-Suk Park; Ki-Seok Yoon; Jung-Hoon Choi; Young-Jin Park; Hee-Goo Youn
Until now, antenna ratio was considered one of the most important parameters for plasma induced damage, and tolerable antenna ratio is very important for circuit designers to guarantee high yield circuits. In this paper, the dependence of plasma induced damage on the gate area is characterized using novel test patterns. The test chip is fabricated using 0.15 /spl mu/m CMOS technology with low-k IMD material. The variation of gate current is used to detect the plasma induced damage. It is shown that the failure rates of transistor increase as the gate area in the transistor increases although the antenna ratio maintains constant. Therefore, to guarantee the reliability of the gate oxide and transistors, we propose that the dependence of plasma induced damage on gate area should be considered when defining the maximum tolerable antenna ratio.
international conference on microelectronic test structures | 2006
Hi-Deok Lee; Hee-Hwan Ji; In-Sik Han; Han-Soo Joo; Dae-Mann Kim; Sung-Hyung Park; Heui-Seung Lee; Won-Joon Ho; Dae-Byung Kim; Ihl-Hyun Cho; Sang-Young Kim; Sung-Bo Hwang; Jeong-Gon Lee; Jin Won Park
Novel test structure is proposed for on-chip evaluation of the crosstalk-induced variation of coupling capacitance in multi-fanout and global interconnect lines. Then, it is experimentally shown that the crosstalk-induced variation of coupling capacitance, /spl Delta/C/sub C/ can be larger than the static coupling capacitance, C/sub C/ for both multi-fanout and global interconnect using the novel on-chip test structures. HSPICE simulation is performed to confirm the experimental data.
Japanese Journal of Applied Physics | 2006
Won-Joon Ho; Sung-Hyung Park; Dong-Sun Kim; In-Shik Han; Hi-Deok Lee; Jae-Yeong Kim; Yu-Be Park; Dae-Byung Kim
A novel back end-of-line (BEOL) process scheme is proposed to improve negative bias temperature instability (NBTI) characteristics through the characterization of the impact of each BEOL process on NBTI of p+ gate metal oxide semiconductor field-effect transistor (PMOSFETs). It is demonstrated that NBTI is strongly dependent on the plasma enhanced nitride (PE-SiN) passivation film and H2 sintering anneal. A new process scheme of N2 annealing instead of H2 annealing prior to PE-SiN deposition is proposed and proven to be highly efficient in improving NBTI without degradation of device performance and n+ gate metal oxide semiconductor (NMOS) hot carrier lifetime.
The Japan Society of Applied Physics | 2007
In-Shik Han; Hee-Hwan Ji; Tae-Gyu Goo; Ook-Sang You; Won-Ho Choi; Min-Ki Na; Ga-Won Lee; Yong-Goo Kim; Sung-Hyung Park; Heui-Seung Lee; Young-Seok Kang; Dae-Byung Kim; Hi-Deok Lee
Oxide in Nano Scale PMOSFET’s In-Shik Han, Hee-Hwan Ji, Tae-Gyu Goo, Ook-Sang You, Won-Ho Choi, Min-Ki Na, Ga-Won Lee, Yong-Goo Kim, Sung-Hyung Park, Heui-Seung Lee, Young-Seok Kang, Dae-Byung Kim and Hi-Deok Lee Dept. of Electronics Engineering, Chungnam National University, Yusong-gu, Daejeon 305-764, Korea Phone: +82-42-821-6868, Fax: +82-42-823-9544, *E-mail: [email protected] Magnachip Semiconductor Inc., Hungduk-gu, Cheongju, Choongbuk, 361-725, Korea