Dae Mann Kim

Monolithic feedback low noise X-band amplifiers using 0.5-/spl mu/m GaAs MESFETs: comparative theoretical study and experimental characterization

Three different feedback low-noise-amplifier (LNA) circuit topologies for simultaneous noise and power matching are theoretically investigated and compared for the X-band application. The smallest minimum noise figure (NF/sub min/) is shown to be achieved by the common source parallel feedback (CSPF) topology, while the common source series feedback (CSSF) topology exhibits the best overall performance. Experimentally, a CSSF three-stage LNA has been fabricated using 0.5-/spl mu/m-gate GaAs MESFETs and systematically characterized. In this LNA circuit, an optimal series feedback for noise figure, gain, and stability is implemented via a proper choice of the short stub length. The size of the fabricated monolithic microwave integrated LNA chip is only 1 mm/sup 2//stage. The measured gain varies from 22.0 to 23.0 dB in the frequency range of 8 to 10 GHz, with good flatness. The input/output voltage standing wave ratios are less than 2 and 1.43, respectively. The noise figure of the three-stage LNA is less than 2.6 dB. These measured data are sufficient for practical applications and are also in good agreement with simulated results.

Characterization of Gate-All-Around Si-NWFET, including R sd , cylindrical coordinate based 1/f noise and hot carrier effects

In this paper, we introduce the cylindrical coordinate based flicker noise model for Silicon NanoWire Field Effect Transistor (Si-NWFET) with Gate-All-Around (GAA) structure. For the accurate extraction of the volume trap density, Nt, with 1/f noise modeling, the parameters which represent the intrinsic channel properties are determined by rejecting the series resistance Rsd effect. Due to the random distribution of traps in Si-NWFETs, the 1/f noise data are obtained by averaging the drain current power spectral density, Sid, for several devices. By using the proposed 1/f model, the extracted volume trap density is compared for three different oxide processes (ISSG/RTO/GNOx) and verified by hot carrier stress test.

Silicon Nanowire Field-Effect Transistor

The field effect transistor was conceived in 1930s and was demonstrated in 1960s. Since then, MOSFET emerged as the mainstream driver for the digital information technology. Because of the simplicity of structure and low cost of fabrication, it lends to a large scale integration for the multifunctional system-on-chip (SOC) applications. Moreover, the device has been relentlessly downsized for higher performance and integration. The physical barriers involved in downscaling the device have prompted the development of process technologies. There has also been the development of device structures from 3D bulk to the gate-all-around nanowire. This chapter is addressed to the discussion of the silicon nanowire field effect transistor (SNWFET). The discussion is carried out in comparison and correlation with the well known theory of MOSFET. The similarities and differences between the two FETs are highlighted, thereby bringing out features unique to SNWFET. Also, an emphasis is placed upon the underlying device physics rather than the device modeling per se. The goal of this chapter is to provide a background by which to comprehend the theories being developed rapidly for SNWFETs.

Highly Reliable 256Mb NOR Flash MLC with Self-Aligned Process and Controlled Edge Profile

We present a comparative investigation of two self-aligned processes, viz. Self-Aligned Poly (SAP) and Self-Aligned STI (SA-STI) for high-density flash memory cells. SAP is shown to lead to narrow erase Vth dispersion and better endurance reliability via the control of oxide edge profile. The erase Vth dispersion is systematically simulated vs. process variations, confirming the sensitive role of edge profile in affecting F-N tunneling current. We also present a successful operation of 256Mb NOR flash MLC, fabricated with a 90 nm technology by SAP process.

Optimal ramped-gate soft programming of over-erased flash EEPROM cells at given current

Presented herein is an efficient simulation technique enabling systematic investigation of the soft programming over-erased flash EEPROM cells. The simulation provides a method by which to find the optimal soft programming technique for given current. The method requires only the cell performance data and allows investigation of the soft programming under various bias conditions. In principle, the methodology can also be used to investigate the programming and erase operations.

Carrier Concentration and Transport

The semiconductor devices operate based upon the charge control, and two factors are involved in the control, namely the concentration and transport of charge carriers. This chapter is addressed to these two basic quantities. The concentration depends upon the doping level, temperature, and other electronic properties of the semiconductor and will be discussed, starting from the Fermi and Boltzmann distribution functions. The carrier transport in semiconductor devices has been attributed primarily to the drift and diffusion. With the downsizing of the semiconductor devices, however, the ballistic transport becomes important as well as tunneling. The transport processes are compactly discussed.

Quantum Wire and Sub-Bands

The quantum mechanics is the basic science supporting the nanotechnology and most of the key concepts operative in the nano electronic devices are derived from it. In terms of the impact made by the theory, the quantum mechanics is one of the greatest theories. In this chapter, the essential features of the quantum mechanics are compactly highlighted, using a few examples. The examples chosen for discussion are directly related to the design and operation of the silicon nano wire field-effect transistor. Specifically, the sub-bands formed in the nano wire are considered, together with the density of states.

P–N Junction Diode: I–V Behavior and Applications

The p–n junction diode is a simple two-terminal solid-state switch, but the theories underlying its operation encompass the central core of the semiconductor device physics. Thus, the I–V modeling of the junction diode should provide a convenient basis for modeling other kinds of semiconductor devices, including the silicon nanowire field effect transistor (SNWFET). Additionally, the p–n junction is used extensively as photodiodes, solar cells, light-emitting and laser diodes, etc. and constitutes a key element of MOSFET. This chapter is addressed to the I–V modeling and applications of the p–n junction diode and should thus provide a general background for discussing SNWFETs in the chapters to follow.

Characterization of silicon nanowire biosensors and solar cells

In this paper, the characteristics of the silicon nanowire (SiNW) based solar cells and biologically modified field-effect transistor (BioFET) are presented and discussed. The pH responses of the BioFETs clearly showed a sensitivity of 40 mV/pH. Also, the lateral shifts of transfer ID-VG curves were observed, depending on the pH value of the solution. Moreover the signal to noise ratio and sensing limit were evaluated, using the low frequency noise data. The solar cells showed higher light absorption and power convergence efficiency (PCE), compared with thin film solar cells. The various structural parameters of the solar cell have been optimized with the use of TCAD simulation and the 15 % improvement of PCE was achieved by adjusting the cell length.

Comparative study of C-V characteristics in Si-NWFET and MOSFET

In this paper, we report the C-V characteristics measured from nanowire capacitor (NWCAP), which has been fabricated by connecting in parallel a large number of identically processed nanowire FETs. By using the C-V data from nanowire devices, we examined the gate voltage response of undoped floating channel. Furthermore, the bias independent overlap capacitance and bias dependent fringing capacitance associated with 1D channel contacting 3D Source/ Drain are extracted. The measured capacitance data are compared with the planar MOS capacitor (MOSCAP) data.