Sung-won Moon

Key challenges for the piezo technology with applications to low form factor thermal solutions

The thermal performance of piezoelectric actuators for cooling in low form factor applications is presented. A significant reduction in thermal resistance is achievable when compared to the baseline natural convection. Comparisons with fans and blowers of similar size result in comparable performance but at greatly reduced power consumption

Thermal Management of a Stacked-Die Package in a Handheld Electronic Device Using Passive Solutions

Various passive thermal management schemes are discussed for a high power component in a handheld electronic device. The validated package and system thermal model based on JEDEC standards and a cell phone mock-up testing were used for the extensive analysis. Also the empirical data was collected to validate thermal improvement predicted by computational fluid dynamics analysis. By using the validated thermal model, the design cycle and time-to-market can be significantly reduced.

Thermal management of a stacked-die package in a handheld electronic device using passive solutions

Various passive thermal management schemes are discussed for a high power component in a handheld electronic device. The validated package and system thermal model based on JEDEC standards and a cell phone mock-up testing were used for the extensive analysis. Also the empirical data was collected to validate thermal improvement predicted by computational fluid dynamics analysis. By using the validated thermal model, the design cycle and time-to-market can be significantly reduced.

Three Dimensional Flow Analysis During Injection Molding Process For Stacked-Die Packages

The three-dimensional numerical simulation has been performed to study mold flow characteristics during injection molding process of stacked die packages. The modeling results revealed that flow front shape is highly non-uniform around the die stack-up units and is dependent on various design parameters including mold cap clearance, mold compound material properties, as well as the die stack-up geometric configurations. It was demonstrated that validated flow model can help guiding the design, material, and process optimization of 3D packaging development.

3-D Numerical Simulation and Validation of Underfill Flow of Flip-Chips

A 3-D flow model, combined with the volume of fluid method, was developed to track capillary driven epoxy flow front, during the underfill process. Die edge effects and fillet spread based on the effect of process parameters were included in this model. Numerical results were validated against flow visualization data. Full field imaging experiments with quartz die were performed to observe flow front as a function of flow time. Development of this new modeling methodology focuses on predicting the capillary underfill flow behavior both in the first level interconnect area between a die and a substrate, and the area surrounding the die. This paper revealed that the edge flow effect contributes to pulling the overall flow front in the bump field area and formation of the fillet spread, which affects the risk associated with underfill delamination in flip chips. A comparative study, which included modeling results and experimental data, clearly indicated that the die edge effect cannot be neglected in order to capture the right trends of flow front shape evolution and an accurate fill time prediction. These comparisons also showed that the model developed in this paper is adequate to approximately simulate the fillet configuration all around the die after encapsulation of flip chips. The modeling methodology developed in this paper provides a fundamental understanding of underfill flow as a function of dispense process parameters, material properties, and package design parameters.

Optimization of packaging materials and design for thermal management in stacked-die packages

Various package level thermal management schemes are discussed. Extensive sensitivity study data of thermally conductive packaging materials such as die adhesive, mold compound, and board level underfill are reviewed on different package architectures by using JEDEC standards. Thermal benefits of heat spreader embedded stacked-die packages are also investigated. By using the validated detailed package thermal model, the design cycle and time-to-market can be significantly reduced

Theta_JC Metrology Development: Fixture Design Modeling

The junction-to-case thermal resistance or Theta_JC is one of the important metrics used to evaluate the performance and reliability of a particular electronic package. Currently, there is no established JEDEC standard for a Theta_JC test fixture. This paper presents the results of computational fluid dynamic (CFD) modeling studies carried out to propose a simple and robust Theta_JC fixture. The theoretical Theta_JC value for a particular package was first obtained assuming idealized conditions. The model was then modified to incorporate actual fixture conditions. The objective is to design a tester fixture that reduces the Theta_JC measurement error, i.e. ideal vs. fixture. The effect of various design parameters on the measured Theta_JC value was investigated. Sensitivity studies included cavity or insulation configuration, cold plate size, thermocouple probe orientation, thermal interface materials, and applied power. Modeling results showed that, regardless of the insulation design, there was considerable heat loss through the test board on which the package was mounted. This resulted in a lower Theta_JC value measured, with errors up to 30%. To reduce the heat loss and measurement error, a heater was mounted at the bottom of the board and maintained at a temperature within 1 to 2°C of the junction temperature. Using this simple approach, the measurement error was reduced to around 6%. From the results of the study, an optimized prototype fixture design is proposed.Copyright