Mathew J. Manusharow

Dual die Pentium D package technology development

This paper describes the technology development for packaging two identical CPU die on one package. Historically, processors involved packaging one die on a package, but with higher performance demands, multiple die products have become necessary. With existing single core die designs, packaging two die in one unit provides a novel way of producing a dual core CPU without designing new silicon. This paper starts with the evolution of dual core CPU from use of two die joined to each other to separate die placed next to each other to the final form of two die placed with a gap. The land grid array (LGA) package technology development was done within the boundary conditions of reuse of existing sockets and enabling solutions. It involved use of higher layer count substrates to allow routing of two die to pre-existing pin-out, modified IHS to accommodate two die in a limited space, and die side components for helping power delivery. The paper describes the details of the substrate technology, routing options and design rules to meet the dual die package requirements that include product performance, substrate manufacturing and assembly and test. The test vehicle definition and design of different structures are described that are new for the dual die scenario. Also limitations based upon compatibility requirements for test lead to creative implementations of those test vehicle structures. The IHS design modifications implemented to fit the two die and to maintain the over all package stack-up are described. Routing and power delivery methodologies in the dual die package architecture are described. Discussed also are how substrate design rules, & collaterals and design process changed and adjusted to the move from a single die to two. The paper then focuses on the multiple challenges faced by the assembly and reliability areas. Single chip package versus dual chip package mechanical stresses are compared. Assembly areas of chip attach, under-fill, and IHS attach are described. The process design rules for UF in dual die case are new compared with the single die case. The challenges of IHS attach and TIM process (including thicknesses) for the two separate die are addressed. Specific challenges encountered for multi-chip packages (MCP) include application of chip attach flux, removal of flux after chip attach as well as voids formed at the TIM to IHS interface. Finally, thermal performances of the dual die package are presented and compared with that of a single die package. The thermal definitions and measurement methods for the dual die package are shown with equivalents to single die case. The thermal benefits of a dual die package prove the advantages of a dual die package in terms of product performance with respect to power dissipation. The future directions of the dual die technology based on the new products on the roadmap are discussed along with some potential areas of focus in the next generation dual die packages

Coreless substrate technology investigation for ultra-thin CPU BGA packaging

Coreless packaging is an attractive option to meet the low z-height requirements typically demanded in low-profile mobile devices. In order to deliver high quality, fully functional assembled coreless packages several aspects of this technology need to be studied to understand the benefits and the drawbacks. Towards realizing this goal, a prototype coreless BGA package for an existing product was designed, fabricated, and characterized for power delivery and IO signal integrity. A comparative study of performance was performed on a 45nm CPU in a coreless BGA package, and compared to the same 45nm CPU in the standard cored BGA. This paper reviews the design strategies implemented and characterization data collected to achieve matched electrical performance with the existing cored package. The paper first makes comparisons between cored and coreless designs and then presents the detailed physical design concepts. Next the paper focuses on electrical performance analysis including both IO performance and power delivery analysis, and then reviews the validation data collected. The results of this study show that the IO performance is comparable between the cored and coreless packages for both microstrip and the stripline routing for both DDR3 and PCI Express Gen 2. Additionally, the power delivery study shows that the expected benefit from the removal of PTHs is compromised in this prototype design due to the removal of die side capacitors and the reduction in the total number of land side capacitors. This made the coreless DC loadline virtually unchanged when compared to the cored package.