Sungchun Jang

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection

An all-digital phase-locked loop with a bang-bang phase-frequency detector (BBPFD) that tracks the optimum loop gain for minimum jitter is proposed. The autocorrelation of the output of BBPFD indicates whether the bang-bang PLL operates in the nonlinear regime or the random noise regime. An adaptive loop gain controller continuously evaluates the autocorrelation of the BBPFD output and adjusts the loop gain to make the autocorrelation zero. The digital loop filter operates at higher than the reference clock frequency to reduce the loop latency and to mitigate the resolution of the digitally controlled oscillator. The prototype chip has been fabricated in a 65-nm CMOS process. The core consumes 5 mW at 2.5 GHz and exhibits root-mean-square jitter of 1.72 ps.

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

This paper presents a 22 to 26.5 Gb/s optical receiver with an all-digital clock and data recovery (AD-CDR) fabricated in a 65 nm CMOS process. The receiver consists of an optical front-end and a half-rate bang-bang clock and data recovery circuit. The optical front-end achieves low power consumption by using inverter-based amplifiers and realizes sufficient bandwidth by applying several bandwidth extension techniques. In addition, in order to minimize additional jitter at the front-end, not only magnitude and bandwidth but also group-delay responses are considered. The AD-CDR employs an LC quadrature digitally controlled oscillator (LC-QDCO) to achieve a high phase noise figure-of-merit at tens of gigahertz. The recovered clock jitter is 1.28 ps rms and the measured jitter tolerance exceeds the tolerance mask specified in IEEE 802.3ba. The receiver sensitivity is 106 and 184 for a bit error rate of 10-12 at data rates of 25 and 26.5 Gb/s, respectively. The entire receiver chip occupies an active die area of 0.75 mm2 and consumes 254 mW at a data rate of 26.5 Gb/s. The energy efficiencies of the front-end and entire receiver at 26.5 Gb/s are 1.35 and 9.58 pJ/bit, respectively.

A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit

As the panel technology continues to offer displays with higher resolution, greater color depth, and increased frame rate, the amount of video data to display driver ICs (DDIs) inside the panel keeps on expanding. Since the conventional intra-panel interfaces with multi-drop configurations, such as RSDS and mini-LVDS, increase the cost of overall systems at high bandwidth, new intrapanel interfaces have been proposed to meet the bandwidth requirement with point-to-point configurations [1–5]. This paper presents a new high-speed video interface that offers significant complexity reduction in the receiver. It is because receivers are integrated in a DDI with relatively slow high-voltage processes, while transmitters in host controllers are implemented with the more advanced deep-submicron processes. Compared to the PLL-based clock recovery circuits in [1–2], the DLL-based data recovery circuit occupies a smaller area with lower power consumption and offers unconditionally stable characteristics along with higher jitter tolerance.

A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process

This brief describes the design of a four-channel 32-Gb/s serial link transmitter with a current-recycling output driver and an on-chip ac-coupled receiver. The proposed output driver significantly reduces power dissipation in the final stage of the transmitter by reusing the natural current flow through the four-channel outputs. It also eliminates the voltage regulation circuit and the current source circuitry for generating low-swing outputs. Since the four-channel outputs are stacked from the ground to the supply rail with different common-mode output levels, the receiver should include an ac-coupling circuit to establish the desired common-mode voltage level for the receive amplifier in each channel. A long-time constant is realized in the ac-coupling circuit with small on-chip capacitors. The prototype chip has been fabricated in the 65-nm low-power CMOS process, and the transmitter supports an output swing of 300 mVpp, diff at a data rate of 8 Gb/s. The four stacked output drivers only consume a total static power of 1.8 mW, and the overall transceiver, including an equalization of 7 dB, exhibits a normalized power dissipation of 2.04 mW/Gb/s.

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

In this paper, a low-phase-noise subharmonically injection-locked all-digital phase-locked loop (PLL) with simplified overall architecture based on a complementary switched injection technique and a sub-sampling bang-bang detector (SSBBPD) is presented. The proposed PLL does not require a timing calibration circuit for phase alignment between the PLL and injection loops. Moreover, instead of a pulse generator, a complementary switched injection technique is used to achieve high frequency (e.g. 5 GHz) injection-locked oscillator. The proposed PLL was implemented in a 65-nm CMOS process on an active area of 0.06mm2, with measurement result showing that it achieves a 484-fs integrated RMS jitter from 1 kHz to 40 MHz at a 5-GHz output frequency while consuming 15.4 mW.

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation

An all-digital spread spectrum clock generator (SSCG) using two-point modulation is presented. To calibrate the gain mismatch between two modulation paths, a background gain calibration method is proposed. To reduce power consumption and design complexity, the bang-bang phase-frequency detector (BBPFD) is used instead of the time-to-digital converter (TDC). The prototype chip has been fabricated in a 65-nm CMOS process and it consumes 6 mW at 2.5 GHz. The measured minimum rms jitter is 1.58 ps.

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm

This paper presents an energy-efficient transmitter driver architecture that is suitable for high-speed operation. By employing an inverter with resistive feedback as a driver cell, the proposed driver topology can overcome the disadvantage of conventional voltage-mode drivers, namely, that the pre-driver power consumption increases as the data rate increases. This driver topology has another advantage that equalization can be easily realized. In order to evaluate the performance of the proposed driver, a PRBS generator, a serializer, and a half-rate clock generator are included in the prototype chip. The proposed driver and equalizer circuit operate reliably at a data rate of up to 20 Gb/s exhibiting an energy efficiency of 0.4 pJ/b for an output swing of 250 mVppd.

Effects of Dietary Protein Levels for Gestating Gilts on Reproductive Performance, Blood Metabolites and Milk Composition

This experiment was conducted to evaluate the effects of dietary CP levels in gestation under equal lysine content on reproductive performance, blood metabolites and milk composition of gilts. A total of 25 gilts (F1, Yorkshire×Landrace) were allotted to 4 dietary treatments at breeding in a completely randomized design, and fed 1 of 4 experimental diets containing different CP levels (11%, 13%, 15%, or 17%) at 2.0 kg/d throughout the gestation. Body weight of gilts at 24 h postpartum tended to increase linearly (p = 0.09) as dietary CP level increased. In lactation, backfat thickness, ADFI, litter size and weaning to estrus interval (WEI) did not differ among dietary treatments. There were linear increases in litter and piglet weight at 21 d of lactation (p<0.05) and weight gain of litter (p<0.01) and piglet (p<0.05) throughout the lactation as dietary CP level increased. Plasma urea nitrogen levels of gilts in gestation and at 24 h postpartum were linearly elevated as dietary CP level increased (p<0.05). Free fatty acid (FFA) levels in plasma of gestating gilts increased as dietary CP level increased up to 15%, and then decreased with quadratic effects (15 d, p<0.01; 90 d, p<0.05), and a quadratic trend (70 d, p = 0.06). There were no differences in plasma FFA, glucose levels and milk composition in lactation. These results indicate that increasing dietary CP level under equal lysine content in gestation increases BW of gilts and litter performance but does not affect litter size and milk composition. Feeding over 13% CP diet for gestating gilts could be recommended to improve litter growth.

A 5.6 GHz LC digitally controlled oscillator with high frequency resolution using novel quadruple resolution varactor

This paper reports a high resolution LC-based digitally controlled oscillator (DCO) using novel quadruple resolution varactor. Proposed DCO has a high frequency resolution and a wide tuning range of 2.2 GHz with a low phase noise at 5.6 GHz. A process and temperature invariant quadruple resolution varactor is proposed to achieve the finest frequency resolution. The proposed varactor achieves one fourth capacitance of a fine varactor, and therefore DCO achieves a very fine frequency resolution with low phase noise. Also, the diode connected circuit makes the proposed varactor robust from the process and temperature variations. The DCO implemented in 0.13 μm CMOS process operates from 3.4 GHz to 5.6 GHz with a resolution from 260 Hz to 0.93 kHz by consuming a power from 5.5 mW to 3.2 mW, respectively. The designed DCO achieves a low phase-noise of −118 dBc/Hz at 1 MHz offset.

A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop

An optical transmitter for driving a Mach-Zehnder (MZ) Interferometer is proposed which incorporates an alldigital phase-locked loop (ADPLL) and a source-series terminated (SST) driver. The proposed optical transmitter is composed of a pattern generator, a clock synthesizer and a modulator driver. The transmitter for an external modulator should drive a large capacitance with a high voltage swing, which requires both large power consumption and area. In this work, the ADPLL is employed for the clock synthesizer to achieve a small area and low power consumption. A high voltage swing over 2 Vdiff-pp with low power is obtained by adopting the SST driver. The implemented transmitter occupies only 0.58 mm2 with power dissipation of 391.6 mW at operating data rate of 21.6 Gb/s.