SungGeun Kim

Full Three-Dimensional Quantum Transport Simulation of Atomistic Interface Roughness in Silicon Nanowire FETs

The influence of interface roughness scattering (IRS) on the performances of silicon nanowire (NW) field-effect transistors is numerically investigated using a full 3-D quantum transport simulator based on an atomistic sp3d5s* tight-binding model. An interface between silicon and silicon dioxide layers is generated in a real-space atomistic representation using an experimentally derived autocovariance function. An oxide layer is modeled in a virtual crystal approximation using fictitious SiO2 atoms. 〈110〉-oriented NWs with different diameters and randomly generated surface configurations are studied. An experimentally observed on-current and threshold voltage are quantitatively captured by the simulation model. The mobility reduction due to IRS is studied through a qualitative comparison of the simulation results with the experimental data.

Engineering Nanowire n-MOSFETs at L-g < 8 nm

As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (Lg) are scaled to lengths shorter than Lg <; 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg <; 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs.

Engineering Nanowire n-MOSFETs at

As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (Lg) are scaled to lengths shorter than Lg <; 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg <; 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs.

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CMOS scaling enabled simultaneous system throughput scaling by concurrent delay, power, and area shrinks with thanks to Moores law. System scaling is getting more difficult with the limitations in interconnect and bandwidth per power as well as the difficulties and cost of monolithic integration. This requires a holistic approach for an optimal balance of performance and power under the limits of technology. This paper covers a portfolio of More Moore technologies for power-aware device enabling value proposition for system scaling - where requirements and gaps will be addressed in the ITRS2.0 roadmap.

More Moore landscape for system readiness - ITRS2.0 requirements

In scaling the dimensions of transistors, gate oxide thicknesses are also scaled. Thinning SiO2 as gate oxide causes gate tunneling. In order to prevent the tunneling, high k dielectric have been used in place of SiO2. Using a thicker dielectric for the same equivalent oxide thickness (EOT) as SiO2 has a negative effect on the device performance through impacting 2D electrostatics. In this work, the effects of high k on double gate (DG) and silicon-on-insulator (SOI) devices are studied. It has been found that using high k for the same EOT can drastically drop the device performance for SOI and DG MOSFETs, with more pronounced degradation for SOI. Also, in thinning the channel thickness, the impact of oxide k variation can be reduced.

Performance degradation due to thicker physical layer of high k oxide in ultra-scaled MOSFETs and mitigation through electrostatics design

As the sizes of MOSFETs become smaller, the role of TCAD tools has increased significantly. Among TCAD tools, drift-diffusion (DD) simulators have been useful in providing insights into the operational principles of MOSFETs. DD simulators are fast due to a low computational burden compared to more sophisticated simulation methods such as full-band quantum transport simulators which cannot handle the volume of the bulk devices. However, as the device sizes become smaller, quantum mechanical (QM) effects render the DD results inaccurate. These QM phenomena are the ballistic resistance, the ballistic transport, the source-to-drain (SD) tunneling and the quantum confinement effects. In this work, these QM effects except the SD tunneling are dealt with such that DD tools can extend their use in modern nanoscale MOSFETs.

Quantum corrected drift-diffusion simulation for prediction of CMOS scaling

As the metal oxide semiconductor field effect transistor (MOSFET) has been scaled down to the nano-meter regime, it has become difficult to further scale the planar type MOSFET [1]. As an alternative device structure, a nanowire transistor has been proposed to the scientific community. Not only that it can suppress the short channel effects in a logic device, it is also a good candidate for a RF device due to its high transconductance and high cut-off frequency [2]. Because of the volume inversion effects, the mobility of electrons in nanowire structures is improved [3], which results in a high transconductance. The capacitance of a nanowire transistor becomes smaller due to a larger effective oxide thickness caused by the volume inversion phenomenon [3]. This paper addresses the effects of interface roughness scattering in a nanowire transistor especially on the cut-off frequency through a full band quantum mechanical simulation [4] of atomistically generated nanowire structure as depicted in Fig. 1.