Surajit Kumar Roy

Scan Chain Design Targeting Dual Power and Delay Optimization for 3D Integrated Circuit

Scan chains are widely used to improve the testability of integrated circuits(ICs) and it is a major issue in circuit testing to optimize test overheads like area, delay andpower. Previous work on scan chain design methodology forthree-dimensional (3D) integrated circuits have been proposed for wire length optimization only. This paper has presented a Genetic Algorithm(GA) based formulation to provide a trade-off between delay and power optimization in scan chain reordering to come up with the ordering of flip-flops on the chain based upon a weighted cost function of delay and power consumption metrics. It has been observed that maximum improvement in power consumption is obtained as 53.78% for ISCAS89 benchmark circuits compared to unordered scan chain.

Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing

Through-silicon-Via (TSV) based three dimensional stacked integrated circuits (3D SICs) testing is a promising area in modern days semiconductor industry. It is seen that the yield of 3D SIC depends on interlayer vertical inter-connectors. Imperfection during the fabrication process results in yield-reducing manufacturing defects. Hence, identification of faulty TSVs and recovery of those faulty TSVs are necessary to improve the yield. In this paper, we have proposed a methodology to test the regular TSVs before bonding (pre-bonding) to identify the faulty TSVs uniquely in reduced test time. Our algorithm also performs better in terms of test time reduction than the previous works presented in the literature. This paper also has discussed the idea of recovery of faulty regular TSVs using redundant TSVs. For a given group ratio, the best possible multiple dependent regular TSVs can be achieved using our proposed scheme for redundancy.

Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing

Design of through-Silicon-Via (TSV) based 3D IC is became feasible recently. Testing of TSVs is an important issue in this respect. It is a challenge to test the TSVs before the bonding of different layers so that the manufacturing defects of TSV can be identified properly. In this paper, we are trying to test the TSVs before bonding. Here we have proposed a heuristic algorithm to locate the faulty TSVs uniquely and at the same time it reduces the test time significantly for locating those faulty TSVs. Simulation results how that our algorithm achieved up to on an average 33% reduction in test time for a 20 TSV network than serial testing approach. Our algorithm also performs better in terms of est time reduction than the previous work present in the literature.

Repairing of faulty TSVs using available number of multiplexers in 3D ICs

Through-silicon via (TSV) based 3D integrated circuit (IC) testing is promising area to the researchers in modern day semiconductor industry. The manufacturing of 3D ICs may produce TSV defects which reduce yield. Recent work has proposed grouping of functional and redundant TSVs such that the faulty functional TSVs are supported by redundant TSVs and multiplexers (MUXs) are used to implement that group. This paper proposes grouping of functional and redundant TSVs such that a functional TSV is supported by redundant TSVs of other groups. We have presented an algorithm that finds the best grouping of functional and redundant TSVs such that maximum recovery of functional TSVs can be achieved with a given number of MUXs.

Power constraints test scheduling of 3D stacked ICs

Core based 3D stacked ICs (3D SICs) is an emerging area in todays semiconductor industry. Traditional testing approaches of 2D IC cannot be applied directly to 3D SICs. In this paper we have addressed a test scheduling approach that try to reduce the overall test application time (TAT) by optimizing the pre-bond and the post-bond test time while reckoning resource conflicts and satisfying power constraints. In addition we proposed distinct algorithms for wafer sort, partial overlapping in package test and rescheduling in package test. Experimental results show that our proposed approach achieved better reduced TAT compared to [1].

Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs

In this paper we have addressed the test infrastructure design for TSV based 3D stacked IC (3D SIC). Each of the die consisting of one or more hard SOCs. Main objective of this work is to design the test architecture for the 3D SIC so that overall test time can be optimized. To prove the efficiency of our proposed algorithm we have considered a 3D stacked IC (SIC) using 5 standard SOCs. Obtained test results show that our proposed solution can achieve up to 59 % reduction in test time compared to the baseline method of sequentially testing all the dies in the stack. We have also shown that increasing the number of test access mechanism (TAM) and through silicon vias (TSVs) help in the reduction of test time but the increase in the number of TAM is unnecessary after a certain limit. In this work we have assumed that the different dies in different layers may consist of two SOCs as opposed to previous work, where each die consists of single SOC.

Faulty TSVs Identification in 3D IC Using Pre-bond Testing

Through-silicon via (TSV) based three-dimensional integrated circuit (3D IC) is gaining remarkable attention in semiconductor industry. The design of 3D IC goes through a complex manufacturing process and testing of TSVs is a critical issue to the researchers. This paper presents an efficient solution for pre-bond TSV testing. The proposed method generates the sequence of test sessions for identifying defective TSVs in a TSV network in reduced test time. Simulation results show the effectiveness of proposed method in terms of test time reduction than the prior works.

Modeling and Analysis of Transient Heat for 3D IC

Three dimensionally integrated circuit (3D IC) is a promising technology in semiconductor industry. 3D IC provides several benefits over the conventional 2D IC. However, thermal issues are major concern due to high power density. So, thermal management is a challenging task for 3D IC. This paper presents a new thermal model for calculating the temperature of a 3D IC accurately. The model is simulated for 3D ICs to study the effects of various parameters like the thermal conductivities of the interface sub-layers, heat sink, power dissipation etc. on temperature of the IC. It is also observed how these parameters affect the transient thermal behavior of the IC.

Recovery of faulty TSVs in 3D ICs

Through-silicon-via (TSV) based three dimensional (3D) integration has evolved as a great area in integrated-circuit (IC) technology. TSV defects may happen due to manufacturing problem 3D IC and the chip is discarded for a single TSV defect. Allocation of redundant TSVs to the faulty TSVs is an attractive solution to recover from TSV defects. Proper grouping of functional and redundant TSVs can enhance the recovery of faulty TSVs. In this paper we have addressed a heuristic approach to find the best possible grouping of functional and redundant TSVs such that the wire length for rerouting redundant TSV is minimized.