Chandan Giri

Scan Chain Design Targeting Dual Power and Delay Optimization for 3D Integrated Circuit

Scan chains are widely used to improve the testability of integrated circuits(ICs) and it is a major issue in circuit testing to optimize test overheads like area, delay andpower. Previous work on scan chain design methodology forthree-dimensional (3D) integrated circuits have been proposed for wire length optimization only. This paper has presented a Genetic Algorithm(GA) based formulation to provide a trade-off between delay and power optimization in scan chain reordering to come up with the ordering of flip-flops on the chain based upon a weighted cost function of delay and power consumption metrics. It has been observed that maximum improvement in power consumption is obtained as 53.78% for ISCAS89 benchmark circuits compared to unordered scan chain.

Data collection point based mobile data gathering scheme with relay hop constraint

Various data gathering techniques using mobile collectors have been developed for energy saving in wireless sensor network. In the sensor field, a mobile collector may traverse within the transmission range of each sensor node to collect data directly from them without any relay. But as the velocity of a mobile collector is low, the data gathering latency may arises which is not desire for many time sensitive applications. To minimize data gathering latency, local data may be aggregated using multi hop transmissions and those collected data may be uploaded to the mobile collector. But, if the number of local relay hop is arbitrarily large then it may increase consumption of energy on packet relays and thus the overall efficiency of mobile data gathering may be reduced. Also, sensor has the limited buffer capacity to store data. So, the relay hop count should be constrained to a certain level to limit the energy consumption at sensors. In this work we have proposed a data collection point based approach that establishes a balance between the energy savings and data gathering latency, which makes an adjustment between the relay hop count for local data aggregation and the moving tour length of the mobile collector. Experimental results show the effectiveness of the proposed approach and provides better average relay hop count than other mobile data gathering schemes of same type.

Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing

Through-silicon-Via (TSV) based three dimensional stacked integrated circuits (3D SICs) testing is a promising area in modern days semiconductor industry. It is seen that the yield of 3D SIC depends on interlayer vertical inter-connectors. Imperfection during the fabrication process results in yield-reducing manufacturing defects. Hence, identification of faulty TSVs and recovery of those faulty TSVs are necessary to improve the yield. In this paper, we have proposed a methodology to test the regular TSVs before bonding (pre-bonding) to identify the faulty TSVs uniquely in reduced test time. Our algorithm also performs better in terms of test time reduction than the previous works presented in the literature. This paper also has discussed the idea of recovery of faulty regular TSVs using redundant TSVs. For a given group ratio, the best possible multiple dependent regular TSVs can be achieved using our proposed scheme for redundancy.

Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing

Design of through-Silicon-Via (TSV) based 3D IC is became feasible recently. Testing of TSVs is an important issue in this respect. It is a challenge to test the TSVs before the bonding of different layers so that the manufacturing defects of TSV can be identified properly. In this paper, we are trying to test the TSVs before bonding. Here we have proposed a heuristic algorithm to locate the faulty TSVs uniquely and at the same time it reduces the test time significantly for locating those faulty TSVs. Simulation results how that our algorithm achieved up to on an average 33% reduction in test time for a 20 TSV network than serial testing approach. Our algorithm also performs better in terms of est time reduction than the previous work present in the literature.

Modelling, detection and diagnosis of multiple faults in cross referencing DMFBs

In recent times digital microfluidics have gained much attention as an emerging technology that provides automation in fluid handling within a miniaturized substrate. Compared to traditional bench-top procedures, microfluidic biochips offer the advantages of low sample and reagent consumption, less likelihood of error due to minimal human intervention, high throughput, and high sensitivity. With the increase in number of bioassays for concurrent operation to be mapped in a single digital microfluidic platform needs for design automation as well as testing and fault diagnosis techniques become highly relevant for better accuracy in results and efficiency in operation. In spite of individual and independent control of electrodes -a new droplet manipulation method based on a “cross-referencing” mode that uses “row” and “columns” to access electrodes has recently come into use. The cross referencing technology largely scales down the control pin number on chip, which not only brings down manufacturing cost but also enables larger number of bioassay integration on a single biochip platform. However, the cross-referencing scheme due to severe electrode interference and other defects can result in faulty operations which in turn cause erroneous results or complete malfunction of the device. In this paper we tried to identify specific types of faults that may occur in cross referencing biochips and developed techniques for detection and location of such faults with the objective of (i) optimum resource utilization and (ii) minimum consumption of time. Testing simulation has been carried out with different size of 2D grids and with different number of test droplets and the corresponding results are found to be encouraging.

A Novel Fuzzy Sensing Model for Sensor Nodes in Wireless Sensor Network

To design an efficient Wireless Sensor Network application one need to understand the behavior of the sensor nodes deployed. To understand the behavior of a systemwe need a very good model, that can represent the system in amore realistic manner. There is a vagueness that we can identify in defining the sensing coverage of any sensor node. The human like reasoning that best suits for this vagueness is the fuzzy reasoning. Here in this paper, we are proposing a fuzzy based model and inference system to best way represent the sensing behavior of sensor nodes. Also, we propose a measure that can be used to check or compare the WSN system performance.

Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning

System-on-a-chip (SOC) uses embedded cores those require a test architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. This approach may also be used for testing of three dimensional stacked integrated circuits (SICs) based on through silicon vias (TSVs). This paper presents an algorithm for minimizing the post bond test time for 3D core-based SOCs under the constraints on the number of TSVs and the available TAM width. Given a TAM width available to test a system-on-a-chip, our algorithm partitions this width into two groups and places the cores of these groups in two layers in 3D design with the goal to optimize the total test time. The experimental results establish the effectiveness of our algorithm.

Fuzzy Logic Based Implementation for Forest Fire Detection Using Wireless Sensor Network

The detection and prevention of forest fire is a major problem now a days. Timely detection allows the prevention units to reach the fire in its initial stage and thus reduce the risk of spreading and the harmful impact on human and animal life. Because of the inadequacy of conventional forest fire detection on real time and monitoring accuracy the Wireless Sensor Network (WSN) is introduced. This paper proposes a fuzzy logic based implementation to manage the uncertainty in forest fire detection problem. Sensor nodes are used for detecting probability of fire with variations during different time in a day. The Sensor nodes sense temperature, humidity, light intensity, CO 2 density and time and send the information to the base station. This proposed system improves the accuracy of the forest fire detection and also provides a real time based detection system as all the input variables are collected in real time basis.

k-Fault Tolerant Topology Control in Wireless Sensor Network

In recent years research in wireless sensor network has gained immense importance. Fault tolerance is an important issue to be addressed in WSN application. Fault tolerance can be achieved at various levels of applications in WSNs. Specifically the categories of applications are: node placement, topology control, target and event detection, data gathering and aggregation and sensor monitoring. This paper proposed a distributed algorithm to control the topology of network to make it fault tolerant.

Repairing of faulty TSVs using available number of multiplexers in 3D ICs

Through-silicon via (TSV) based 3D integrated circuit (IC) testing is promising area to the researchers in modern day semiconductor industry. The manufacturing of 3D ICs may produce TSV defects which reduce yield. Recent work has proposed grouping of functional and redundant TSVs such that the faulty functional TSVs are supported by redundant TSVs and multiplexers (MUXs) are used to implement that group. This paper proposes grouping of functional and redundant TSVs such that a functional TSV is supported by redundant TSVs of other groups. We have presented an algorithm that finds the best grouping of functional and redundant TSVs such that maximum recovery of functional TSVs can be achieved with a given number of MUXs.