Sven Eriksson

Application of switched-current technique to algorithmic DA- and AD-converters

As possible applications of the switched current technique, algorithmic DA- and AD-converters are presented. The design shows advantages in small power dissipation (3 mW) and in small area because of the use of very few MOS devices. Multichannel or more complex design does not increase the area too much if the possibility of sharing the same current sources is used. The circuit is implemented using a 2- mu m double-metal, N-well technology through MOSIS.<<ETX>>

A power-saving technique for bit-serial DSP ASICs

The bit-serial processing technique arises to be a competitor of the traditional bit-parallel processing technique to implement DSP ASICs, because the bit-serial implementation of DSP ASICs usually results in small communication cost and compact processing elements. However, shift registers are usually used to realize delays required by the DSP algorithms. Long shift registers consume a lot of power for they are clocked at very high frequency. More troublesome is that the power associated with driving a lot of clocked transistors has to be supplied by the clock lines (not power supply lines), which may cause clock distribution problem. In this paper, we propose a power-saving technique without speed penalty by getting rid of unnecessary data shifting and long shift registers. All the delay elements in the traditional long shift registers are realized by DRAM-alike memory cells and data is not shifted but accessed by using shared cyclical address decoders. The measurement of a test chip indicates a power saving by 4 times when we need to use 15 16-bit shift registers. More power saving is expected when we need more shift registers for large DSP ASICs.<<ETX>>

A low voltage wave SI filter implementation using improved delay elements

In this paper we present a low voltage wave switched-current filter. In order to enhance the performance, delay elements with an improved clock-feedthrough cancellation technique are used. A test filter has been implemented in a standard CMOS process. The chosen filter and circuit structure is shown to be suitable for automatic layout generation.<<ETX>>

Low-voltage low-power switched-current circuits and systems

This paper presents low-voltage low-power switched-current circuits and systems. Novel class AB configuration and common-mode feedforward are the essence. A delay line, memory cell, oversampling A/D converter, and chopper-stabilized oversampling A/D converter were designed and implemented. Measurement results are presented as well.<<ETX>>

Z-domain synthesis of switched-capacitor LDI ladder filters

A Z-domain two-port flowgraph synthesis method for switched-capacitor (SC) ladder filters is described. This approach for the design of lossless-dielectric-integrator (LDI) ladder filters is, compared to other methods, general and flexible. The proposed method can lead to a design of a locally nonreciprocal and globally reciprocal network. Both conventional switched-capacitor ladder filters and new switched-capacitor realizations can be designed using this approach. It is concluded that the advantages of these novel SC filter realizations can be exploited when the filters are implemented using integrated MOS technology.<<ETX>>

Two-stage decimation filter design technique for oversampling /spl Delta/-/spl Sigma/ A/D converters

Practical considerations restrict the usefulness of all but the simplest comb filters as the first-stage decimators in oversampling delta-sigma A/D converters due to the large oversampling ratios. A design technique is thereupon presented for two-stage decimators in oversampling delta-sigma A/D converters. This design technique takes into account the noise shaping in the delta-sigma modulator and the requirements of the whole A/D converter in order to optimize the decimator. The optimum decimators are also derived in order to achieve the maximum resolution performance.<<ETX>>

Audio /spl Sigma//spl Delta/-modulator implementation using class AB compact switched current memory cells

A second order bitstream /spl Sigma//spl Delta/ modulator, using compact switched current memory circuits (CMCs) have been implemented. The structure uses the commonly used integrator structure, and calculations predetermine -57-dB noise floor for a 20 kHz bandwidth and 1-MHz clock frequency. A chip is under fabrication.<<ETX>>