Sven Peyer

Detailed Routing Algorithms for Advanced Technology Nodes

We present algorithms for routing in advanced technology nodes, used by BonnRoute (BR) to obtain efficient and almost design rule clean wire packings and pin access solutions. Designs with dense standard cell libraries in presence of complex industrial design rules, with a special focus on multiple patterning lithography are considered. The key components of this approach are a multilabel interval-based shortest path algorithm for long on-track connections, and a dynamic program for computing packings of pin access paths and short connections between closely spaced pins. The multilabel path search implementation is very general and is driven with different labeling rules, allowing to trade-off runtime against accuracy in terms of obeyed design rules. We combine BR with an industrial router for cleaning up the remaining design rule violations, and demonstrate superior results over that industrial router in our experiments in terms of wire length, number of vias, design rule violations, and runtime.

Optimizing product yield using manufacturing defect weights

Yield of 45nm products can be optimized by adjusting how the router is run. While forcing wiring to upper levels adds wire length and increases the number of vias, sensitivity to random defects is reduced. Wire spreading does not improve yield for 45nm products.