Swamy Muddu

Modeling Edge Placement Error Distribution in Standard Cell Library

In this work we present a predictive model for the edge placement error (EPE) distribution of devices in standard library cells based on lithography simulations of selective test patterns. Poly-silicon linewidth variation in the sub-100nm technology nodes is a major source of transistor performance variation (e.g., Ion and Ioff) and circuit parametric yield. It has been reported that significant part of the observed variation is systematically impacted by the neighboring layout pattern within optical proximity. Design optimization should account for this variation in order to maximize the performance and manufacturability of chip designs. We focus our analysis on standard library cells. In the past the EPE characterization was done on simple line array structures. However, the real circuit contexts are much more complex. Standard library cells offer a nice balance of usability by the designers and modeling complexity. We first construct a set of canonical test structures to perform lithography simulations using various OPC parameters and under various focus and exposure conditions. We then analyze the simulated printed image and capture the layout-dependent characteristics of the EPE distribution. Subsequently, our model estimates the EPE distribution of library cells based on their layout. In contrast to a straight-forward simulation of the library cells themselves, this approach is computationally less expensive. In addition the model can be used to predict the EPE distribution of any library cells and not limited to those that are simulated. Also, since the model encapsulates the details of lithography, it is easier for designers to integrate into design flow.

Interconnect modeling for improved system-level design optimization

Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level optimizations, such as network-on-chip (NoC) synthesis, are inaccurate in the presence of deep-submicron effects. In this paper, we propose new, highly accurate models for delay and power in buffered interconnects; these models are usable by system-level designers for existing and future technologies. We present a general and transferable methodology to construct our models from a wide variety of reliable sources (Liberty, LEF/ITF, ITRS, PTM, etc.). The modeling infrastructure, and a number of characterized technologies, are available as open source. Our models comprehend key interconnect circuit and layout design styles, and a power-efficient buffering technique that overcomes unrealities of previous delay-driven buffering techniques. We show that our models are significantly more accurate than previous models for global and intermediate buffered interconnects in 90 nm and 65 nm foundry processes - essentially matching signoff analyses. We also integrate our models in the COSI-OCC synthesis tool and show that the more accurate modeling significantly affects optimal/achievable architectures that are synthesized by the tool. The increased accuracy provided by our models enables system-level designers to obtain better assessments of the achievable performance/power/area tradeoffs for (communication-centric aspects of) system design, with negligible setup and overhead burdens.

Impact of Gate-Length Biasing on Threshold-Voltage Selection

Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly reduce their leakage current for a small delay penalty. The technique was shown to work effectively with multi-threshold-voltage assignment, the only mainstream approach for runtime leakage reduction. Typically, designers use threshold voltages selected by the foundries to optimize their designs. Higher threshold-voltage devices, that are less leaky but slow, are assigned to non-critical paths and lower threshold-voltage devices, that are fast but leaky, are assigned to critical paths. In this paper we study the effect of modifying threshold voltages set by the foundry on leakage reduction achieved on three large, real-world designs. We assess the impact of the availability of gate-length biasing on threshold voltage selection. We achieve comparable leakage reductions when foundry-set dual threshold voltages are used with biasing than when foundry-set triple threshold voltages are used without biasing. Our results indicate that leakage reductions can be improved if threshold voltages are carefully chosen considering the availability of gate-length biasing. We also observe that foundry-set threshold voltages are not optimal for achieving best possible leakage reductions

Resist Heating Dependence on Subfield Scheduling in 50kV Electron Beam Maskmaking

In high-voltage electron beam lithography, most of the beam energy is released as heat and accumulates in the local area of writing. Excessive heat causes changes in resist sensitivity, which in turn causes significant critical dimension (CD) variation. Previous methods for reducing CD distortion caused by resist heating include usage of lower beam currents, increased delays between electron flashes, and multi-pass writing. However, all these methods lower mask writing throughput. This leads to increased mask writing cost, which is increasingly becoming a major limiting factor to semiconductor industry productivity. In this paper, we propose a new method for minimizing CD distortion caused by resist heating. Our method performs simultaneous optimization of beam current density and subfield writing order. Simulation experiments show that, compared to previous methods, the new subfield scheduling method leads to significant reductions in resist temperature with unchanged mask writing throughput. Alternatively, subfield scheduling can be coupled with the use of higher beam current densities, leading to increased writing throughput without increasing CD distortion.

Subfield scheduling for throughput maximization in electron-beam photomask fabrication

Resist heating is one of the largest contributors to critical dimension (CD) distortion in electron beam photomask fabrication. Previous methods for reducing CD variation caused by resist heating include lower beam currents, increased delays between electron flashes, and writing in multiple passes. However, all these methods lower mask writing throughput. This leads to increased mask writing cost, which is increasingly becoming a major limiting factor to semiconductor industry productivity. In this work, we investigate a new degree of freedom for mitigating CD distortion caused by resist heating. By optimizing the sequence in which subfields are being written, it is possible to reduce CD variability caused by resist heating, without significantly increasing the mask writing time.

Detailed placement for leakage reduction using systematic through-pitch variation

We present a novel detailed placement technique that accounts for systematic through-pitch variations to reduce leakage. Leakage depends nearly exponentially on linewidth (gate length), and even small variations in linewidth introduce large variability in leakage. A substantial fraction of linewidth variation is systematic with respect to the device layout context. Detailed placement changes context of the devices that are near the cell boundaries and can be used to reduce leakage. Our approach modifies the placement of cells in small windows such that contexts that reduce leakage are created. During this optimization, cells are partitioned into rows and then placed in rows using a traveling salesman problem formulation.

A Novel Metric for Interconnect Architecture Performance

We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given interconnect architecture (IA). This new metric, the rank of an IA, is a single number that gives the number of connections in the WLD that meet a specific target delay when embedded in the IA. A dynamic programming algorithm is presented to exactly compute the rank of an IA with respect to a given WLD within practical runtimes. We use our new IA metric to quantitatively compare impacts of geometric parameters as well as process and material technology advances. For example, we observe that 42% reduction in Miller coupling factor achieves the same rank improvement as a 38% reduction in inter-layer dielectric permittivity for a 1 M gate design in the 130 nm technology.

Modeling OPC complexity for design for manufacturability

Increasing design complexity in sub-90nm designs results in increased mask complexity and cost. Resolution enhancement techniques (RET) such as assist feature addition, phase shifting (attenuated PSM) and aggressive optical proximity correction (OPC) help in preserving feature fidelity in silicon but increase mask complexity and cost. Data volume increase with rise in mask complexity is becoming prohibitive for manufacturing. Mask cost is determined by mask write time and mask inspection time, which are directly related to the complexity of features printed on the mask. Aggressive RET increase complexity by adding assist features and by modifying existing features. Passing design intent to OPC has been identified as a solution for reducing mask complexity and cost in several recent works. The goal of design-aware OPC is to relax OPC tolerances of layout features to minimize mask cost, without sacrificing parametric yield. To convey optimal OPC tolerances for manufacturing, design optimization should drive OPC tolerance optimization using models of mask cost for devices and wires. Design optimization should be aware of impact of OPC correction levels on mask cost and performance of the design. This work introduces mask cost characterization (MCC) that quantifies OPC complexity, measured in terms of fracture count of the mask, for different OPC tolerances. MCC with different OPC tolerances is a critical step in linking design and manufacturing. In this paper, we present a MCC methodology that provides models of fracture count of standard cells and wire patterns for use in design optimization. MCC cannot be performed by designers as they do not have access to foundry OPC recipes and RET tools. To build a fracture count model, we perform OPC and fracturing on a limited set of standard cells and wire configurations with all tolerance combinations. Separately, we identify the characteristics of the layout that impact fracture count. Based on the fracture count (FC) data from OPC and mask data preparation runs, we build models of FC as function of OPC tolerances and layout parameters.

Design-of-experiments based design rule optimization

Design rules (DRs) are the primary abstraction between design and manufacturing. The optimization of DRs to achieve the correct tradeoff between scaling and yield is a key step in developing a new technology node. In this work we propose a design-of-experiments based framework to optimize DRs, where layouts are generated for different DR values using compaction. By analyzing the impact of DRs on layout scaling, we propose a novel Boolean minimization based approach to reduce the number of layouts that need to be generated through compaction. This methodology provides an automated approach to analyze several DRs simultaneously and discover area-critical DRs and DR interactions. We apply this methodology to middle-of-line (MOL) and Metal1 layer design rules for a commercial 20nm process. Our methodology results in 10 - 105 x reduction in the number of layouts that need to be generated through compaction, and demonstrates the impact of MOL and Metal1 DRs on the area of some standard cell layouts.

Improving critical dimension accuracy and throughput by subfield scheduling in electron beam mask writing

Resist heating in high-voltage, high-throughput electron beam (e-beam) mask write is a significant source of critical dimension (CD) distortion. Excessive heating on the reticle determines changes in resist sensitivity, which in turn cause significant CD variation. CD distortions on the reticle are replicated onto the wafer with increased magnitude as determined by the mask error enhancement factor (MEEF). As designs enter the sub-90nm regime, CD variation has a significant impact on performance, performance variation, and product yield. Previous methods for reducing CD distortion include usage of lower e-beam current density, increased delays between electron flashes, and multipass writing. However, all of these methods lower mask writing throughput, which is increasingly becoming a limiting factor in semiconductor industry productivity. In this paper, we propose a novel method for minimizing CD distortion and maximizing mask writing throughput. By scheduling the writing of subfields, we perform simultan...