Abde Ali Kagalwalla

Power Variability in Contemporary DRAMs

Technology scaling has led to significant variability in chip performance and power consumption. In this work, we measured and analyzed the power variability in dynamic random access memories (DRAMs). We tested 22 double date rate third generation (DDR3) dual inline memory modules (DIMMs), and found that power usage in DRAMs depends on both operation type (write, read, and idle) as well as data, with write operations consuming more than reads, and 1s in the data generally costing more power than 0s. Temperature had little effect (1-3%) across the C to 50 C range. Variations were up to 12.29% and 16.40% for idle power within a single model and for different models from the same vendor, respectively. In the scope of all tested 1 gigabyte (GB) modules, deviations were up to 21.84% in write power. Our ongoing work addresses memory management methods to leverage such power variations.

Design-Aware Defect-Avoidance Floorplanning of EUV Masks

Fabricating defect-free mask blanks remains a major obstacle for the adoption of EUV lithography. We propose a simulated annealing based gridded floorplanner for single-project multiple-die reticles that minimize the design impact of buried defects. Our results show a substantial improvement in mask yield with this approach. For a 60-defect mask, our approach can improve the mask yield from 0% to 26%. If additional design information is available, it can be exploited for more accurate yield computation and further improvement in mask yield to 99.6%. These improvements are achieved with a limited area overhead of less than 0.2% on the exposure field. Our simulation results also indicate that around 10%-30% mask yield improvement is possible as a result of floorplanning compared to shifting the entire mask pattern. Our floorplanner can tolerate a defect position error (due to mask blank inspection tools) of 0.25 μm with just a 2% reduction in yield. The impact of defect dimensions and multilayer EUV patterning on the viability of floorplanning is also analyzed in this paper.

Design-aware mask inspection

Mask inspection has become a major bottleneck in the manufacturing flow taking up as much as 30% of the total manufacturing time [15]. In this work we explore techniques to improve the reticle inspection flow by increasing its design awareness. We develop an algorithm to locate non-functional features in a post-OPC layout with 100% accuracy without using any design information. Using this, and timing information of the design (if available), we assign a minimum size defect to each reticle feature that could cause the design to fail. The criticality of various reticle features is then used to partition the reticle such that each partition is inspected at a different pixel size and sensitivity so that the false+nuisance defect count is reduced without missing any critical defect. Up to 4X improvement in false+nuisance defect count is observed with our technique resulting in up to 55% improvement in first pass yield coming from reduction in nuisance defects and substantial reduction in defect review load.

Design-Aware Mask Inspection

Mask inspection has become a major bottleneck in the manufacturing flow taking up as much as 40% of the total mask manufacturing time. In this paper, we explore techniques to improve the reticle inspection flow by increasing its design awareness. We develop an algorithm to locate nonfunctional features in a postoptical proximity correction layout without using any design information. Using this, and the timing information of the design (if available), the smallest defect size that could cause the design to fail is assigned to each reticle feature. The criticality of various reticle features is then used to partition the reticle such that each partition is inspected at a different pixel size and sensitivity so that the false and nuisance defect count is reduced without missing any critical defect. We also develop an analytical model to estimate the false and nuisance defect count. Using those models, our simulation results show that this design-aware mask inspection can reduce the false and nuisance defect count for a critical polysilicon layer from 80 defects down to 49 defects, leading to substantial reduction in defect review load. We also develop a model to estimate first pass yield (FPY) and show that our method can improve the FPY for a polysilicon layer from 11% to 30%. Apart from the polysilicon layer, the potential benefit of this approach is analyzed for active, contact and all the metal/via layers.

Benchmarking of mask fracturing heuristics

Aggressive resolution enhancement techniques such as inverse lithography (ILT) often lead to complex, non-rectilinear mask shapes which make mask writing extremely slow and expensive. To reduce shot count of complex mask shapes, mask writers allow overlapping shots, due to which the problem of fracturing mask shapes with minimum shot count is NP-hard. The need to correct for e-beam proximity effect makes mask fracturing even more challenging. Although a number of fracturing heuristics have been proposed, there has been no systematic study to analyze the quality of their solutions. In this work, we propose a new method to generate benchmarks with known optimal solutions that can be used to evaluate the suboptimality of mask fracturing heuristics. We also propose a method to generate tight upper and lower bounds for actual ILT mask shapes by formulating mask fracturing as an integer linear program and solving it using branch and price. Our results show that a state-of-the-art prototype [version of] capability within a commercial EDA tool for e-beam mask shot decomposition can be suboptimal by as much as 3.7× for generated benchmarks, and by as much as 3.6× for actual ILT shapes.

Comprehensive defect avoidance framework for mitigating EUV mask defects

Defect avoidance methods are likely to play a key role in overcoming the challenge of mask blank defects in EUV lithography. In this work, we propose a novel EUV mask defect avoidance method. It is the first approach that allows exploring all the degrees of freedom available for defect avoidance (pattern shift, rotation and mask floorplanning). We model the defect avoidance problem as a global, non-convex optimization problem and then solve it using a combination of random walk and gradient descent. For a 8nm polysilicon layer of an ARM Cortex M0 layout, our method achieves 60% point better mask yield compared to prior art in defect avoidance for a 40-defect mask.

EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts

Despite the use of mask defect avoidance and mitigation techniques, finding a usable defective mask blank remains a challenge for Extreme Ultraviolet Lithography (EUVL) at sub-10nm node due to dense layouts and low CD tolerance. In this work, we propose a pattern shift-aware metric called critical density, which can quickly evaluate the robustness of EUV layouts to mask defects (300-1300x faster than Monte Carlo, with average mask yield root mean square error (RMSE) ranging from 0.08%-6.44%), thereby enabling design-level mask defect mitigation techniques. Our experimental results indicate that reducing layout regularity improves the ability of layouts to tolerate mask defects via pattern shift.

Design-of-experiments based design rule optimization

Design rules (DRs) are the primary abstraction between design and manufacturing. The optimization of DRs to achieve the correct tradeoff between scaling and yield is a key step in developing a new technology node. In this work we propose a design-of-experiments based framework to optimize DRs, where layouts are generated for different DR values using compaction. By analyzing the impact of DRs on layout scaling, we propose a novel Boolean minimization based approach to reduce the number of layouts that need to be generated through compaction. This methodology provides an automated approach to analyze several DRs simultaneously and discover area-critical DRs and DR interactions. We apply this methodology to middle-of-line (MOL) and Metal1 layer design rules for a commercial 20nm process. Our methodology results in 10 - 105 x reduction in the number of layouts that need to be generated through compaction, and demonstrates the impact of MOL and Metal1 DRs on the area of some standard cell layouts.

Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects

Abstract. Defect avoidance methods are likely to play a key role in overcoming the challenge of mask blank defectivity in extreme ultraviolet (EUV) lithography. In this work, we propose an innovative EUV mask defect avoidance method. It is the first approach that allows exploring all the degrees of freedom available for defect avoidance (pattern shift, rotation and mask floorplanning). We model the defect avoidance problem as a global, nonconvex optimization problem and then solve it using a combination of random walk and gradient descent. For a 8-nm polysilicon layer of an ARM Cortex M0 layout, our method achieves a 60% point better mask yield compared to prior art in defect avoidance for a 40-defect mask. We show that pattern shift is the most significant degree of freedom for improving mask yield. Rotation and mask floorplanning can also help improve mask yield to a certain extent.

Effective model-based mask fracturing for mask cost reduction

The use of aggressive resolution enhancement techniques like multiple patterning and inverse lithography (ILT) has led to expensive photomasks. Growing mask write time has been a key reason for the cost increase. Moreover, due to scaling, e-beam proximity effects can no longer be ignored. Model-based mask fracturing has emerged as a useful technique to address these critical challenges by allowing overlapping shots and compensating for proximity effects during fracturing itself. However, it has been shown recently that heuristics for model-based mask fracturing can be suboptimal by more than 1.6× on average for ten real ILT shapes, highlighting the need for better heuristics. In this work, we propose a new model-based mask fracturing method that significantly outperforms all the previously reported heuristics. The number of e-beam shots of our method is 23% less than a state-of-the-art prototype version of capability within a commercial EDA tool for e-beam mask shot decomposition (PROTO-EDA) for ten ILT mask shapes. Moreover, our method has an average runtime of less than 1.4s per shape.