Swaraj Bandhu Mahato

Atomistic approach to variability of bias-temperature instability in circuit simulations

A blueprint for an atomistic approach to introducing time-dependent variability into a circuit simulator in a realistic manner is demonstrated. The approach is based on previously proven physics of stochastic properties of individual gate oxide defects and their impact on FET operation. The proposed framework is capable of following defects with widely distributed time scales (from fast to quasi-permanent), thus seamlessly integrating random telegraph noise (RTN) effects with bias temperature instability (BTI). The use of industry-standard circuit simulation tools allows for studying realistic workloads and the interplay of degradation of multiple FETs.

Impact of transistor aging on RF low noise amplifier performance of 28nm technology: Reliability assessment

Transistor reliability has become one of the major concerns in reliable circuit design in advanced CMOS nanometer technology. Transistor aging can have a significant impact on the performance of the RF frontend circuits. In this paper, the impacts of transistor aging on a RF low noise amplifier (LNA) are studied. In this work, single-ended cascode LNA with source inductive degeneration and LC folded-cascode LNA test circuits are used to study the transistor aging effect. The noise figure (NF) and the gain, critical performance parameters of a LNA are shown to be degradation-sensitive. It is shown that the noise figure of the LNA is significantly increased and the gain of the LNA is decreased by the aging effect using a 28nm technology. The optimum gate bias point and the cascode structure have been shown as design guidelines to make the LNA more reliable.

Kernel-based crosstalk quantification and analysis of a CMOS image sensor

Inter-pixel crosstalk degrades the point spread function (PSF) of a scientific imager which affects quantitative interpretation of scientific image data. Compared to the CCD, crosstalk is larger in the CMOS image sensor. This problem is challenging due to constant downscaling of the CMOS technology and pixel size. In this work, we parametrized the inter-pixel crosstalk and also modeled it as an empirically quantifiable kernel. A CMOS image sensor with 6 μm pixel pitch is measured. Evidently the crosstalk value can change with the PSF centroid position inside a pixel, primarily due to the spatial extent of the beam, which causes some optical generation in the surrounding pixels. We demonstrate a crosstalk measurement method and its spatial variation with respect to the spot position. This sub-pixel scanning is conducted to measure any crosstalk variation with respect to the sub-pixel spot position. Notable asymmetry on the crosstalk value between rows and columns as well as in the four corners of the POI is observed. This variation shows how the signal is shared at the pixel boundaries. Several POIs (Pixel of interest) over the scan region are measured to analyze the crosstalk variations.

Two-dimensional MTF characterization of a large format CMOS detector

We are characterizing a 7638 x 5004 front-side illuminated CMOS detector for astronomical application. Mod- ulation Transfer Function (MTF) of a detector is considered as an important figure of merit for accurate target positioning in astronomy. It states the upper limit of the image quality. MTF knowledge also provides a better understanding of the design trade-off. In this work, two-dimensional (2D) sub-micrometer scanning method is used to extract 2D MTF profile of our CMOS detector with a pixel pitch of 6μm. Our optical measurement setup focuses a collimated beam onto the imaging surface with a microscope objective. The spot was scanned in a raster over a single pixel. We generate an oversampled point spread function (PSF) of the detector which contains sub-pixel elements. 2D MTF map is calculated from the measured oversampled PSF. This 2D MTF map is used to characterize the resolving ability of our detector. We analyze the importance of the 2D MTF map to describe the full pixel MTF of the CMOS pixel having low fill-factor. 1D MTFs are calculated from the 2d MTF to do a quantitative comparison of the MTF in horizontal and vertical directions. This study emphasizes advantages and necessity of the 2D MTF for CMOS detector performance analysis, especially for anisotropic resolution.

Characterization of the per-pixel dark current and activation energy of a large format CMOS image sensor

In past decade, CMOS imagers are becoming increasingly popular in scientific imaging like astronomy. Large format image sensors are the detector of choice for the wide field imaging. The circuit integration capability of the CMOS imager is considered as an advantage while inducing the temperature variation over the sensor area. Dark current of the image sensor is strongly temperature-dependent signal and one of the limiting factors of the low light imaging. Here, we present per-pixel dark current measurement results and analysis of a 7638 x 5004 pixels front-side illuminated CMOS image sensor with a pixel pitch of 6 μm. In this work, global non- uniformity induced by the on-chip temperature variation is controlled by the Peltier junction device. This paper reports results of our dark current study for the temperature range 233 to 273 K with exposure of 0 to 300 s. A reasonably low dark current of 0.014 e-/pixel/s is achieved at 233 K temperature. The dark current spatial distributions at different temperatures are presented. We extracted the activation energy for the dark current in this lower temperature range. Using the Arrhenius law, dark current data analysis shows the Meyer-Neldel Relationship (MNR) between the Arrhenius pre-factor and the apparent activation energy.

A novel technique to characterize the spatial intra-pixel sensitivity variations in a CMOS image sensor

To understand the scientific imaging capability, one must characterize the intra-pixel sensitivity variation (IPSV) of the CMOS image sensor. Extracting an IPSV map contributes to an improved detector calibration that allows to eliminate some of the uncertainty in the spatial response of the system. This paper reports the measurement of the sub-pixel sensitivity variation and the extraction of the 2D IPSV map of a front-side illuminated CMOS image sensor with a pixel pitch of 6 µm. Our optical measurement setup focuses a collimated beam onto the imaging surface with a microscope objective. The spot was scanned in a raster over a single pixel and its immediate neighbors in order to probe its response at selected (sub-pixel) positions. In this work we introduced a novel technique to extract the IPSV map by fitting (forward modeling) the measured data to a mathematical model of the image, generated in a single pixel that allows for a spatially varying sensitivity.

Noise optimization of the source follower of a CMOS pixel using BSIM3 noise model

CMOS imagers are becoming increasingly popular in astronomy. A very low noise level is required to observe extremely faint targets and to get high-precision flux measurements. Although CMOS technology offers many advantages over CCDs, a major bottleneck is still the read noise. To move from an industrial CMOS sensor to one suitable for scientific applications, an improved design that optimizes the noise level is essential. Here, we study the 1/f and thermal noise performance of the source follower (SF) of a CMOS pixel in detail. We identify the relevant design parameters, and analytically study their impact on the noise level using the BSIM3v3 noise model with an enhanced model of gate capacitance. Our detailed analysis shows that the dependence of the 1/f noise on the geometrical size of the source follower is not limited to minimum channel length, compared to the classical approach to achieve the minimum 1/f noise. We derive the optimal gate dimensions (the width and the length) of the source follower that minimize the 1/f noise, and validate our results using numerical simulations. By considering the thermal noise or white noise along with 1/f noise, the total input noise of the source follower depends on the capacitor ratio CG/CFD and the drain current (Id). Here, CG is the total gate capacitance of the source follower and CFD is the total floating diffusion capacitor at the input of the source follower. We demonstrate that the optimum gate capacitance (CG) depends on the chosen bias current but ranges from CFD/3 to CFD to achieve the minimum total noise of the source follower. Numerical calculation and circuit simulation with 180nm CMOS technology are performed to validate our results.

Offset measurement method for accurate characterization of BTI-induced degradation in opamps

Bias temperature instability (BTI) has become one of the major concerns in reliable circuit design in advanced CMOS nanometer technology. It can have a significant impact on the performance of analog building blocks. To understand the effect of BTI in analog circuits, an accurate measurement of circuit parameter degradation by BTI has become very necessary. This paper proposes a measurement scheme of the input offset degradation of an operational transconductance amplifier (OTA) due to the BTI effect. Conventional offset measurement techniques do not take into account the BTI recovery. Therefore, the proposed scheme is targeted to measure degradation during the stressing to avoid relaxation. The concept behind the scheme is to present the offset degradation as a function of the propagation delay degradation. Simulation results are shown for the measurement circuit.

Recent trends in CMOS reliability: From individual traps to circuit simulations

Summary form only given. In recent years, researchers are building models relying on a wide variety of data that can be extracted from software repositories, concerning for example characteristics of source code changes, or be related to bug introduction and fixing. Software repositories also contain a huge amount of non-structured information, often expressed in natural language, concerning communication between developers, as well as tags, commit notes, or comments developers produce during their activities. This keynote illustrates, on the one hand, how explanatory or predictive models build upon software repositories could be enhanced by integrating them with the analysis of communication among developers. On the other hand, the keynote warns agains perils in doing that, due to the intrinsic imprecision and incompleteness of such a textual information, and explains how such problems could, at least, be mitigated.