Sylvain Barraud

Effect of discrete impurities on electron transport in ultrashort MOSFET using 3D MC simulation

This paper discusses the influence of the channel impurity distribution on the transport and the drive current in short-gate MOSFETs. A careful description of electron-ion interaction suitable for the case of discrete impurities has been implemented in a three-dimensional particle Monte Carlo simulator. This transport model is applied to the investigation of 50-nm MOSFET operation. The results show that a small change in the number of doping impurities or in the position of a single discrete impurity in the inversion layer may significantly influence the drain current. This effect is not only related to threshold voltage fluctuations but also to variations in transport properties in the inversion layer, especially at high drain voltage. The results are analyzed in terms of local fluctuations of electron velocity and current density. In a set of fifteen simulated devices the drive current I/sub on/, determined at V/sub GS/=V/sub DS/=0.6 V, is found to vary in a range of 23% according to the position of channel impurities.

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

A detailed study of performance in uniaxially strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial strained-SOI (sSOI) substrate is presented. Two-dimensional strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. An improvement of electron mobility in sSOI NW scaled down to 10-nm width is successfully demonstrated (+55 % with respect to SOI NW) due to remaining uniaxial tensile strain. This improvement is maintained even by using hydrogen annealing to form an Omega gate. For short gate length, a strain-induced ION gain as high as +40% at LG = 45 nm is achieved for a multiple-NW active pattern.

A new backscattering model giving a description of the quasi-ballistic transport in nano-MOSFET

A backscattering model suitable for compact modeling of nanoscale MOSFET is developed within the Landauer flux-scattering theory. To describe the quasi-ballistic transport, a new backscattering model based on the accurate determination of ballistic and backscattering probabilities along the channel is developed. This model is based on a careful analysis of transport in device using Monte Carlo simulation. This model allows us to display the main physical quantities along the channel and to accurately describe the quasi-ballistic transport and its effects on current-voltage characteristics.

Short-range and long-range Coulomb interactions for 3D Monte Carlo device simulation with discrete impurity distribution

Abstract A 3D Monte Carlo (MC) device simulation model is developed for the treatment of discrete random dopant distribution in sub-100 nm MOSFET. The electron–ion (e–i) interaction model is based on a suitable description of long-range Coulomb interaction included by a particle–mesh (PM) calculation method and short-range interaction taken into account by a scattering mechanism. Attention is given to the correct definition of the short-range domain and scattering model. This new approach is validated by computing the low-field electron drift mobility in Si by means of MC simulation of 3D resistors in the doping concentration range of 10 15 –6.4×10 19 cm −3 . A good agreement is found between calculation and experimental data at 300 K.

Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

A detailed study of performance in uniaxially-strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial SSOI substrate is presented. 2D strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. For the first time, an improvement of electron mobility in SSOI NW scaled down to 10nm width has been successfully demonstrated (+55% with respect to SOI NW). This improvement is maintained even by using H2 annealing used for Ω-Gate. On short gate length, a strain-induced Ion gain as high as 40% at LG=45nm is achieved for multiple-NWs active pattern.

A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

Continuous CMOS improvement has been achieved in recent years through strain engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down, conventional strain elements (as embedded stressors, stress liners) are loosing their effectiveness [1]. The use of strained materials for the channel to boost performance is thus essential. In this paper, we present an original multilevel evaluation methodology for stress engineering design in next-generation power-efficient devices. Fully-Depleted-Silicon-On-Insulator (FDSOI) is chosen as the ideal test vehicle, as it offers the advantage of sustaining significant stress within the channel without plastic relaxation (the thin channel staying below the critical thickness [2]). Starting from 3D mechanical simulations and piezoresistive coefficient data, an original, simple, physically-based model for holes/electrons mobility enhancement in strained devices is developed. The model is calibrated on physical measurements and electrical data of state-of-the-art devices. Non-Equilibrium Greens Function (NEGF) quantum simulations of holes/electrons stress-enhanced mobility give physical insights into mobility behavior at large stress (~3GPa). Finally, the new strained-enhanced mobility model is introduced in an industrial compact model [3] to project evaluation at the circuit level.

Contact resistances in trigate and FinFET devices in a non-equilibrium Green's functions approach

We compute the contact resistances Rc in trigate and FinFET devices with widths and heights in the 4–24 nm range using a Non-Equilibrium Greens Functions approach. Electron-phonon, surface roughness, and Coulomb scattering are taken into account. We show that Rc represents a significant part of the total resistance of devices with sub-30 nm gate lengths. The analysis of the quasi-Fermi level profile reveals that the spacers between the heavily doped source/drain and the gate are major contributors to the contact resistance. The conductance is indeed limited by the poor electrostatic control over the carrier density under the spacers. We then disentangle the ballistic and diffusive components of Rc and analyze the impact of different design parameters (cross section and doping profile in the contacts) on the electrical performances of the devices. The contact resistance and variability rapidly increase when the cross sectional area of the channel goes below ≃50 nm2. We also highlight the role of the charg...

First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm

We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si_1-xGe_x (x=0, 0.2, 0.25) nanowires, Si_0.7Ge_0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W^-3 dependence of ON current (I_ON) per wire. The fabricated devices exhibit higher I_ON than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

Study of piezoresistive properties of advanced CMOS transistors: Thin film SOI, SiGe/SOI, unstrained and strained Tri-Gate Nanowires

We hereby present an exhaustive extraction and study of piezoresitive (PR) coefficients in advanced CMOS transistors. In particular, we have evidenced the dependence with channel thickness and channel material compositions (SiGe with various Ge contents). Moreover we report for the first time the measurement of PR coefficient on uniaxially strained and unstrained Tri-Gate Nanowires transistors.

Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length

We have fabricated hybrid channel Ω-gate CMOS nanowires (NWs) with strained SiGe-channel (cSiGe) p-FETs and Si-channel n-FETs. An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si. Effectiveness of cSiGe channel is also evidenced for ultra-scaled p-FET NWs (gate length LG=15 nm) with +90% ION current improvement.