Syuso Fujii

A 45-ns 16-Mbit DRAM with triple-well structure

The authors describe a 16-Mb DRAM (dynamic RAM) fabricated with a triple-well CMOS technology that enables optimum choice of well bias. With this technology, an optimized chip architecture, and a p-channel load word-line bootstrap driver incorporating a predecoder a 45-ns row-access-strobe access time is achieved. The memory cell is in a quarter-pitched arrangement combined with an interdigitated bit-line/shared-sense-amplifier scheme. This overcomes the difficulty of defining capacitor-plate poly in a scaled-down trench or buried-stacked-capacitor cell. The output waveform of the RAM is shown. The features of the 16M DRAM are summarized. It is capable of fast page, static column, or nibble operation and -*1- or *4-bit organization, determined by the choice of bonding configuration.<<ETX>>

A 1Mb CMOS DRAM with fast page and static column modes

1Mw X l b CMOS DRAM with 24ns column address access time, 56ns row access time, 30mA average active current and 0.3mA CMOS standby current will be described. The chip has been fabricated with a 1 . 2 ~ triple-polysilicon N-well CMOS process. The RAM uses a half Vcc bit line precharge technique with a complementary capacitor coupled dummy cell (C3DC) and a bit-line level generator to reduce by 50% the bit-line discharge current and also to improve the sensing margin. Figure 1 shows sense circuit schematics and pulse diagrams. At the beginning of an active cycle, the selected word line is bootstrapped above the Vcc level to obtain a large signal from the memory cell for speed and to store full Vcc potential in the memory cell for a high sensing margin. At the same time, one of the dummy word-line pairs, precharged to a half Vcc level, goes to full Vcc level, while the other to Vss level, setting the reference bit line to correct mid-point level. During the active cycle after sensing, one of the bit line pair is kept at full Vcc level by a P-channel restoring circuit, while the other is kept at Vss level by an Nchannel sense amplifier. At the end of the active cycle, bit line pairs as well as dummy word lines are short-circuited and equalized to the half Vcc level without discharge. In addition, the half Vcc level (VBL) generated by the bit-line level generator is supplied to these bit-line pairs and dummy word lines to eliminate unbalance due to the leakage current during RAS precharge cycle. The bit-line equalizing technique in the RAS precharge cycle permits access to the high speed memory cell. Another feature of the development is the use of partial activation of the memory array that is divided into 4 blocks. Two blocks out of four are selectively activated in each cycle, leaving the other two blocks in a standby condition. Therefore, the power dissipation due to the bit-line discharge/precharge operation is reduced to about 1/4 by the half Vcc bit-line precharge and the partial activation. A substrate bias generator with a VBB level detection circuit controls the ring oscillator. The VBB level goes down quickly at power on time, t o increase the latch-up immunity, and the low standby current is realized at a stable state. The use of clocked CMOS circuits and asynchronous CMOS static circuits with address transition detectors for high speed operation is shown in Figure 2. The flexibility inherent to CMOS circuitry permits the inclusion of fast page and the static column modcs with a metal mask option. Laser redundancy circuits improve fabrication yield without speed degradation and minimize the number of fuse links. Four spare columns and four spare rows are available to replace defective bits, rows and columns.

A 50-μA standby 1M x 1/256K×4 CMOS DRAM with high-speed sense amplifier

A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.

A 17-ns 4-Mb CMOS DRAM

A 17-ns nonaddress-multiplexed 4-Mb dynamic RAM (DRAM) fabricated with a pure CMOS process is described. The speed limitations of the conventional DRAM sensing technique are discussed, and the advantages of using the direct bit-line sensing technique are explained. A direct bit-line sensing technique with a two-stage amplifier is described. One readout amplifier is composed of a two-stage current-mirror amplifier and a selected readout amplifier is activated by a column decoder output before the selected word line rises. The amplifier then detects a small bit-line signal appearing on a bit-line pair immediately after the word-line rise. This two-stage amplification scheme is essential to improving access time, especially in the case of a CMOS process. The high sensitivity of the readout amplifier is discussed, and the electrical features and characteristics of the fabricated DRAM are reported. >

A 1-Mbit CMOS DRAM with fast page mode and static column mode

A 1-Mb words/spl times/1-bit CMOS dynamic RAM fabricated with an advanced n-well CMOS technology is described. More than 2.2 million devices are integrated on a 62.5 mm/SUP 2/ silicon chip by utilizing an n-channel memory cell of triple-level poly Si structure and a 1.2-/spl mu/m feature size VLSI process. Novel CMOS circuit design techniques such as the half V/SUB cc/ bitline precharge scheme are successfully applied to realize the excellent performance combination of high-speed operation and low-power dissipation. The CMOS peripheral circuitry is capable of the new operating functions, fast page mode, or static column mode with metal mask options. The typical RAS access time is 56 ns, the active current is 30 mA at a 190-ns cycle time, and the standby current is 0.2 mA.

A 50&#181;A standby 1MW &#215; 1b/256KW &#215; 4b CMOS DRAM

A single mask set DRAM architecture with a 1MW×1b or 256KW×4b organization, selectable by bonding configurations, will be discussed. With a CMOS half Vcccc generator, a standby current of 50μA has been achieved. A triple layer polysilicon N-well measuring 3.24μm2has resulted in a chip size of 4.4×12.3mm2with an access time of 56ns.

A 34ns 256Kb DRAM

A 256K × 1b MOS DRAM, using power circuits and MoSi<inf>2</inf>gate transistors, will be reported. Division of the chip into eight blocks results in 34ns<tex>\overline{CAC}</tex>access time, 94ns<tex>\overline{RAC}</tex>and 170mW active power.