Masaki Ogihara

A 45-ns 16-Mbit DRAM with triple-well structure

The authors describe a 16-Mb DRAM (dynamic RAM) fabricated with a triple-well CMOS technology that enables optimum choice of well bias. With this technology, an optimized chip architecture, and a p-channel load word-line bootstrap driver incorporating a predecoder a 45-ns row-access-strobe access time is achieved. The memory cell is in a quarter-pitched arrangement combined with an interdigitated bit-line/shared-sense-amplifier scheme. This overcomes the difficulty of defining capacitor-plate poly in a scaled-down trench or buried-stacked-capacitor cell. The output waveform of the RAM is shown. The features of the 16M DRAM are summarized. It is capable of fast page, static column, or nibble operation and -*1- or *4-bit organization, determined by the choice of bonding configuration.<<ETX>>

A 17-ns 4-Mb CMOS DRAM

A 17-ns nonaddress-multiplexed 4-Mb dynamic RAM (DRAM) fabricated with a pure CMOS process is described. The speed limitations of the conventional DRAM sensing technique are discussed, and the advantages of using the direct bit-line sensing technique are explained. A direct bit-line sensing technique with a two-stage amplifier is described. One readout amplifier is composed of a two-stage current-mirror amplifier and a selected readout amplifier is activated by a column decoder output before the selected word line rises. The amplifier then detects a small bit-line signal appearing on a bit-line pair immediately after the word-line rise. This two-stage amplification scheme is essential to improving access time, especially in the case of a CMOS process. The high sensitivity of the readout amplifier is discussed, and the electrical features and characteristics of the fabricated DRAM are reported. >