T. Fukano

Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V

This paper reports on low-power and high-speed resistive switching of a Ti-doped NiO memory, which is based on the switching mechanism of the redox reactions in a filamentary conductive path. A small reset current of less than 100 muA was achieved by controlling the gate voltage of a cell transistor, which acts as an excellent current limiter in the set operation. A fast reset time of less than 5 ns was achieved by doping the Ti into the NiO film. Ti is thought to be effective to not only stabilize the reset process by forming an oxygen reservoir, but also to suppress the abnormal set phenomenon during the reset operation due to the formation of strong Ti-O bonds. Moreover, stable pulse switching with a large resistance change ratio has been successfully demonstrated using a unipolar voltage source of less than 3 V.

Si single electron tunneling transistor with nanoscale floating dot stacked on a Coulomb island by self-aligned process

We fabricated a Si single electron tunneling transistor which has a nanoscale floating dot gate stacked on a Coulomb island by a self-aligned process. This device exhibits drain current (Id) oscillations due to the Coulomb blockade effect and quantized threshold voltage (Vth) shifts resulting from a single electron tunneling from the channel to the floating dot gate. The high on/off current ratio of the Id oscillation combined with the quantized Vth shifts leads to the possibility of developing ultralow power consumption memory.

50-nm gate Schottky source/drain p-MOSFETs with a SiGe channel

We propose new SiGe channel p-MOSFETs with germano-silicide Schottky source/drains (S/Ds). The Schottky barrier-height (SBH) for SiGe is expected to be low enough to improve the injection of carriers into the SiGe channel and, as a result, current drivability is also expected to improve. In this work, we demonstrate the proposed Schottky S/D p-MOSFETs down to a 50-nm gate-length. The drain current and transconductance are -339 /spl mu/A//spl mu/m and 285 /spl mu/S//spl mu/m at V/sub GS/=V/sub DS/=-1.5 V, respectively. By increasing the Ge content in the SiGe channel from 30% to 35%, the drive current. and transconductance can be improved up to 23% and 18%, respectively. This is partly due to the lower barrier-height for strained Si/sub 0.65/Ge/sub 0.35/ channel than those for strained Si/sub 0.7/Ge/sub 0.3/ channel device and partly due to the lower effective mass of the holes.

21 psec switching 0.1 /spl mu/m-CMOS at room temperature using high performance Co salicide process

In this paper we report a record of 0.1 /spl mu/m-CMOS switching delay of 21 psec per gate at room temperature operation. Good subthreshold characteristics are achieved for 0.1 pm gate length n-MOS and p-MOS. Conventional Ti, Pt and Co self-aligned silicide process (salicide) degraded the 0.1 pm CMOS switching delay because the gate sheet resistances increased at fine-line. In contrast, Co salicide with TiN capping process achieved a low gate resistance of 5 /spl Omegasq at all over gate length. And it allowed the high speed operation at the sub quarter micron gate length region.<<ETX>>

Epitaxially grown base transistor for high-speed operation

We developed a transistor with a very thin base to improve the speed of the intrinsic bipolar transistor. The epitaxially grown base transistor, or EBT, consists of an in-situ boron-doped epitaxial base layer that is photochemically grown, Photoepitaxy, with a low growth temperature of about 650°C, enables us to fabricate a very thin heavily doped layer. Our EBT has a base 65 nm thick and a peak boron concentration of 1 × 1019/cm3. Compared with high-speed bipolar transistors reported to date, EBTs have half the base width and ten times the peak boron concentration. The maximum current gain was about 500. Despite the very thin base, the Early voltage was about 70 V because of the high boron concentration. The EBT is potentially capable of very high-speed operation if combined with a structure that minimizes parasitic capacitance.

Room temperature operation of Si single-electron memory with self-aligned floating dot gate

Reports on a new Si single-electron memory device comprised of a narrow channel field effect transistor (FET) having an ultra-small selfaligned floating dot gate and its ability to exhibit clear, single-electron memory effects at room temperature.

Giga-bit DRAM cells with low capacitance and low resistance bit-lines on buried MOSFETs and capacitors by using bonded SOI technology-reversed stacked capacitor (RSTC) cell

This paper describes a reversed-stacked-capacitor (RSTC) cell for Giga-bit DRAMs, where a storage capacitor and a MOSFET are reversed by using chemical-mechanical-polishing (CMP) and bonded-SOI technology. The virtual flat surface at the bottom of the MOSFET is made into a real surface by polishing. The bit-lines and metal wirings are realized on the flat surface with low-aspect-ratio contact holes throughout the whole chip. This cell structure is suitable for not only Giga-bit DRAMs but also embedded DRAMs. A test memory array is fabricated with a 64 Mbit DRAM design rule. Both capacitance and resistance of bit-lines decreased by a factor of two with this RSTC cell compared to the conventional shielded-bit-line STC cells. The bit-lines are placed far from word-lines and cell-capacitors. The bit-lines are made of low resistivity materials after all the high-temperature processes have been finished.

Si single-electron tunneling transistor with nanoscale floating dot stacked on a Coulomb island by self-aligned process

We studied experimentally and theoretically in detail a Si single-electron tunneling transistor which has a nanoscale floating dot gate stacked on a Coulomb island by a self-aligned process. At 4.2 K, this device exhibits drain current (Id) oscillations due to the Coulomb blockade effect besides the quantized threshold voltage (Vth) shifts with a hysteresis resulting from a single-electron tunneling between the channel and the floating dot gate. The periodicity of the Coulomb oscillation, the voltage separation (ΔVw) between the adjacent two voltages where the Vth shift occurs are consistent with those calculated from the geometrical consideration. The Coulomb oscillation disappeared at room temperature, however, the quantized Vth shifts and hysteresis curves, which are basic operations of single-electron memory, were observed up to room temperature. The fluctuation of electron number in the floating dot was theoretically analyzed at room temperature and we obtained consistent results with the experiments...

Reduction of Reset Current in NiO-ReRAM Brought about by Ideal Current Limiter

In this paper, we fabricated 1T1R NiO-ReRAM test circuits based on 0.18 mum CMOS technology and observed notable suppression of I_reset by imposing current compliance I_comp using a cell transistor. Reducing the stray capacitance between Pt/NiO/Pt and the cell transistor used as a current limiter is crucial in this issue. This enabled the systematic measurement of I_comp dependence of l_reset for I_comp < 1 mA and I_reset ap I_comp was observed for 150 muA les I_comp les950 muA.

Multiple self-alignment MOS technology (MUSA/MOST)

Multiple self-alignment MOS technology, MUSA/MOST, has been developed to achieve higher packing density and higher performance for Si MOSFETs. The minimum mask feature of 1.5 µm allows fabrication of a 0.5 µm channel length FET in an active device area as narrow as 3.5 µm. This significantly reduces parasitic capacitances and increases device packing density. Metal and metal-silicide can be employed to form the gate and source/drain electrodes, respectively, resulting in reduction of VLSI circuit wiring-delays. The fabricated ring oscillator with enhancement drivers and depletion loads of MUSA/MOSTs exhibited a propagation delay of 540 ps/stage under the 2 µm design rule.