T. J. Chin

Clocking and circuit design for a parallel I/O on a first-generation CELL processor

A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. A clock-tracking architecture suppresses reference jitter to achieve 6.4Gbit/s/link operation at 21.6mW/Gbit/s. SOI effects on analog circuits, in particular high-speed receivers, are addressed to achieve a receiver sensitivity of /spl plusmn/12mV at 6.4Gbit/s with BER <10/sup -14/ measured using 7b PRBS data.

A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell

An asymmetric memory interface cell with 32 bidirectional data and four unidirectional request links operating at 16 Gb/s per link is implemented in TSMC 65 nm CMOS process technology. Timing adjustment and equalization circuits for both memory read and write are on the controller to reduce the memory cost. Each link operates at a maximum rate of 16 Gb/s with sufficient and comparable margins in both directions at a BER of 10-12. The measured energy efficiency for the controller interface cell is 13 mW/Gb/s under nominal operating conditions.

Clocking circuits for a 16Gb/s memory interface

8 GHz clocking circuits for a 16 Gb/s/pin asymmetric memory interface [1] are described. A combination of an LC-PLL and a ring-PLL achieves improved jitter performance for multiple phase outputs with a wide frequency range. A direct phase mixer and a digitally controlled duty-cycle corrector (DCC) are time-multiplexed between transmitter (TX) and receiver (RX), thereby reducing area and power. The prototype chip implemented in a 65 nm CMOS technology has measured 734 fs RJ (rms) at the TX output when operating at 16 Gb/s.

A 16Gb/s 65nm CMOS transceiver for a memory interface

A transceiver for a memory controller operating at 16 Gb/s per link is implemented in 65 nm CMOS process. Timing calibration, equalization and diagnostic circuits for both memory read and write are on the controller to optimize the overall system performance and cost. A 5-tap TX FIR and a continuous time RX equalizer with active inductor loads are employed. The transceiver also includes a diagnostic circuit which can add a programmable DC differential voltage offset and produce actual eye diagrams for both write and read links. It is demonstrated that each link can operate at 16 Gb/s with a timing margin of 0.19 UI at a BER of 10-12.

Low-skew clock distribution using zero-phase-clock-buffer DLLs

Clock distribution continues to be a challenging task in digital clocked systems. In a typical clocking architecture (Fig. 9.2.1, top), a phase-locked loop (PLL) produces the desired phase/frequency, and an H-tree clock distribution network distributes the generated clock signal to multiple sections (A to D) on the die. Mismatch between the H-tree branches, such as mismatch in wires and clock buffers (B1 to B6), introduce skew between different clock ends CLKA to CLKD. Mesh clocking network may result in skew reduction at the expense of power consumption. To alleviate the power overhead, resonant clocking techniques have been successfully demonstrated in both single-ended [1] and differential [2] clock distributions. At resonance, the global wire capacitance can be driven by fewer numbers of buffers with reduced strength, leading to reduced global clock power consumption and improved power supply induced jitter (PSIJ). Injection-locked clock distribution was proposed in [3] as alternative low-power solutions with the capability of de-skewing. Further, [4] provides a comparative study between resonant clock distribution and injection-locked clock distribution with the goal of achieving minimum jitter. However, none of the above has been focusing on minimizing clock skew.

An 8Gb/s/link, 6.5mW/Gb/s memory interface with bimodal request bus

An 8Gb/s/link power optimized controller memory interface is implemented in TSMC 40nm G CMOS process. It is composed of 32 differential data links to support 32GB/s payload. The bimodal drivers of the request bus enable support of both 12 bits of 2Gb/s/link single-ended RSL (Rambus Signaling Level) for existing XDRTM memory and 6 bits of 8Gb/s/link differential signaling for next generation XDR2TM memory. A 1-tap pre-emphasis transmitter equalizer and a source-degenerated linear receiver equalizer with offset trim are added on this controller interface to reduce signal swing and thus minimize power in both write and read directions. The measurement results show that with a 100mV swing (peak-to-peak single-ended) for the read and a 150mV swing for the write, the timing margin is greater than 0.25UI at a BER of 10-12 with real memory transactions. The measured power efficiency for the PHY is 6.5mW/Gb/s.