Kambiz Kaviani

Clocking and circuit design for a parallel I/O on a first-generation CELL processor

A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. A clock-tracking architecture suppresses reference jitter to achieve 6.4Gbit/s/link operation at 21.6mW/Gbit/s. SOI effects on analog circuits, in particular high-speed receivers, are addressed to achieve a receiver sensitivity of /spl plusmn/12mV at 6.4Gbit/s with BER <10/sup -14/ measured using 7b PRBS data.

A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell

An asymmetric memory interface cell with 32 bidirectional data and four unidirectional request links operating at 16 Gb/s per link is implemented in TSMC 65 nm CMOS process technology. Timing adjustment and equalization circuits for both memory read and write are on the controller to reduce the memory cost. Each link operates at a maximum rate of 16 Gb/s with sufficient and comparable margins in both directions at a BER of 10-12. The measured energy efficiency for the controller interface cell is 13 mW/Gb/s under nominal operating conditions.

A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver

This paper describes a low-power receiver front-end in a bidirectional near-ground source-series terminated (SST) interface implemented in a 40-nm CMOS process, which supports low-common mode differential NRZ signaling up to 16-Gb/s data rates. The high-speed operation is enabled by utilizing a common-gate amplifier stage with replica transconductance impedance calibration that accurately terminates the channel in the presence of receiver input loading. The near-ground low-impedance receiver also incorporates common-mode gain cancellation and in-situ equalization calibration to achieve reliable data reception at 16 Gb/s with better than 0.4 mW/Gb/s power efficiency over a memory link with more than 15 dB loss at the Nyquist frequency.

Clocking circuits for a 16Gb/s memory interface

8 GHz clocking circuits for a 16 Gb/s/pin asymmetric memory interface [1] are described. A combination of an LC-PLL and a ring-PLL achieves improved jitter performance for multiple phase outputs with a wide frequency range. A direct phase mixer and a digitally controlled duty-cycle corrector (DCC) are time-multiplexed between transmitter (TX) and receiver (RX), thereby reducing area and power. The prototype chip implemented in a 65 nm CMOS technology has measured 734 fs RJ (rms) at the TX output when operating at 16 Gb/s.

A 16Gb/s 65nm CMOS transceiver for a memory interface

A transceiver for a memory controller operating at 16 Gb/s per link is implemented in 65 nm CMOS process. Timing calibration, equalization and diagnostic circuits for both memory read and write are on the controller to optimize the overall system performance and cost. A 5-tap TX FIR and a continuous time RX equalizer with active inductor loads are employed. The transceiver also includes a diagnostic circuit which can add a programmable DC differential voltage offset and produce actual eye diagrams for both write and read links. It is demonstrated that each link can operate at 16 Gb/s with a timing margin of 0.19 UI at a BER of 10-12.

A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS

A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor inter-symbol interference (ISI) cancellation at high data-rate operations.

Characterization of a low-power 6.4 Gbps DDR DIMM memory interface system

A memory system that meets the bandwidth, power efficiency, and capacity needs of future computing systems is presented in this paper. A 6.4 Gbps single-ended DDR memory interface for the controller and the DRAM was designed in a 28-nm CMOS process for a main memory system with dual-rank DIMMs. The architecture features a novel clocking scheme, per-pin timing adjustment, dynamic point-to-point signaling topology, and near ground signaling. The system V-T budget simulations and the characterization results of the fabricated memory interface are presented.

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching

A dynamic rate adjustable interface is designed a 40-nm LP CMOS process. On-the-fly dynamic rate change is enabled by an all-digital frequency multiplier that detects a reference frequency change, and accordingly provides 4× multiplied clock without any idle time. The clock multiplier, along with matched source synchronous clocking and clock equalization, allows blind reference clock shifting to scale the data rate from 1.6 to 6.4 Gb/s within 6.125ns without idle time or bit errors during transitions. The interface efficiency is 2.6 mW/Gb/s @6.4 Gb/s & 3.4 mW/Gb/s @3.2 Gb/s when using reduced clock swing and external transmitter swing at the reduced data rates.

Design and analysis of 12.8 Gb/s single-ended signaling for memory interface

The design of a high-speed single-ended parallel interface using conventional package and board technologies is presented. The system uses asymmetrical architecture where the equalization and timing adjustment circuits for both memory WRITE and READ transactions are on the controller to reduce the memory cost. The analysis and optimization steps employed to mitigate the effect of inter-symbol interference, crosstalk, and supply noise are discussed. The impact of data encoding techniques on system timing margin is also investigated. The designed single-ended signaling was able to achieve a reliable communication at a data rate of 12.8 Gbps over a graphics channel. Several of the noise reduction techniques were also verified with measurement made on a prototype system.

An 8Gb/s/link, 6.5mW/Gb/s memory interface with bimodal request bus

An 8Gb/s/link power optimized controller memory interface is implemented in TSMC 40nm G CMOS process. It is composed of 32 differential data links to support 32GB/s payload. The bimodal drivers of the request bus enable support of both 12 bits of 2Gb/s/link single-ended RSL (Rambus Signaling Level) for existing XDRTM memory and 6 bits of 8Gb/s/link differential signaling for next generation XDR2TM memory. A 1-tap pre-emphasis transmitter equalizer and a source-degenerated linear receiver equalizer with offset trim are added on this controller interface to reduce signal swing and thus minimize power in both write and read directions. The measurement results show that with a 100mV swing (peak-to-peak single-ended) for the read and a 150mV swing for the write, the timing margin is greater than 0.25UI at a BER of 10-12 with real memory transactions. The measured power efficiency for the PHY is 6.5mW/Gb/s.