Chris Madden

Simulation and Analysis of Random Decision Errors in Clocked Comparators

Clocked comparators have found widespread use in noise sensitive applications including analog-to-digital converters, wireline receivers, and memory bit-line detectors. However, their nonlinear, time-varying dynamics resulting in discrete output levels have discouraged the use of traditional linear time-invariant (LTI) small-signal analysis and noise simulation techniques. This paper describes a linear, time-varying (LTV) model of clock comparators that can accurately predict the decision error probability without resorting to more general stochastic system models. The LTV analysis framework in conjunction with the linear, periodically time-varying (LPTV) simulation algorithms available from RF circuit simulators can provide insights into the intrinsic sampling and decision operations of clock comparators and the major contribution sources to random decision errors. Two comparators are simulated and compared with laboratory measurements. A 90-nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73 mVrms for dc inputs, matching simulation results with a short channel excess noise factor ¿ = 2.

Clocking and circuit design for a parallel I/O on a first-generation CELL processor

A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. A clock-tracking architecture suppresses reference jitter to achieve 6.4Gbit/s/link operation at 21.6mW/Gbit/s. SOI effects on analog circuits, in particular high-speed receivers, are addressed to achieve a receiver sensitivity of /spl plusmn/12mV at 6.4Gbit/s with BER <10/sup -14/ measured using 7b PRBS data.

Advanced Modeling and Accurate Characterization of a 16 Gb/s Memory Interface

As the input/output (I/O) data rate increases to several gigabits per second, determining the performance of high-speed interfaces using conventional simulation and measurement techniques is becoming very challenging. The models of the interconnects have to be broadband and accurate to represent high frequency and second-order effects such as frequency dependence of dielectric losses and surface roughness. The large and small signal behaviors of the transmitter and receiver circuitries have to be correctly represented in link analysis. In addition, the system simulation needs to properly capture the interactions between the circuits and interconnect subsystems to optimize the overall system. However, determining the values of the critical link parameters and their correlations can be complicated. Some of the key parameters are not deterministic and some cannot be observed directly. A combined modeling and measurement approach is indispensable to determine the performance of high-speed links. This paper presents the modeling and characterization techniques employed in the design and verification of a 16 Gb/s bidirectional asymmetrical memory interface. Direct frequency and time-domain methods as well as indirect techniques based on bit-error-rate testing are used to model and determine important link parameters. Complex de-embedding procedures are utilized to extract parameters from externally observed data. On-chip measurements are also used to complement off-chip instrumentation and accurately measure the true performance of the link. The modeling and characterization of prototypes are also discussed and model-to-hardware correlations are presented at component and system levels. Based on both simulation and measurement results, the behavioral model of the complete system is constructed and statistical simulation technique is used to predict the yield and performance at low bit error rate.

Design and characterization of a 12.8GB/s low power differential memory system for mobile applications

This paper describes the design and characterization of a low power differential memory interface targeted for mobile applications. The initial design of the memory interface achieves 2.7 to 4.3GB/s data bandwidth and consumes 3.3mW/Gb/s at 4.3GB/s operation. The design allows two x16 stacked dies to be fit into a 12mm PoP package, achieving a 12.8GB/s aggregated data bandwidth based on 3.2Gb/s per pin. A low swing signaling based on a voltage-mode differential driver is reviewed and its performance is analyzed. We demonstrate that, compared to LPDDR2 memory interface based on single-ended signaling, the differential memory interface overcomes most of channel related issues such as crosstalk and SSO noise and provides a very clean channel response. Thus, the resulting extra system margin can be used to compensate for extra timing jitter and system noise, enabling lower power and lower system cost. To evaluate the impact of timing jitter and system noise to system performance, a statistical link modeling and simulation methodology is employed. Two test systems are built based on wirebond-based Package-on-Package (PoP) and BGA-based Chip-to-Chip (C2C) module to characterize the memory system performance and to validate the memory statistical link model. The correlation result showed a good agreement in the system bit error rates (BER) between measurement and simulation.

Jitter Amplification Considerations for PCB Clock Channel Design

Jitter Amplification is a real concern in the design of PCB clock channels if the frequency of the clock is high and the PCB trace is relatively long. In this paper, we confirm the earlier finding of clock channel jitter amplification [1], using a multiple edge response (MER) simulation method instead of jitter impulse response for the channel. However, we show that both white Random Jitter (wRJ) and Sinusoidal Jitter (SJ) amplification are a function of the signal loss in the channel, and as such, are reduced significantly with equalization. Furthermore, simulated CMOS Tx RJ, which is dominated by its low frequency components, is amplified less than is wRJ, even for channels with >20dB signal loss. Measurement results are correlated with simulations for 2-6 GHz clocks on a channel containing 24-inches of PCB trace.

Investigating the Impact of Supply Noise on the Jitter in Gigabit I/O Interfaces

Minimizing the jitter due to supply noise is the most important design goal for the power delivery system of highspeed interfaces. We present a detailed analysis of supply noise induced jitter in a high-speed interface. We first simulate the supply noise spectrum generated in the interface. We then measure the sensitivity of the interface circuits to noise as a function of noise frequency. Next, we analyze the jitter spectrum by combining these two parameters. Based on this analysis, we observe large jitter contributions at medium frequencies. This is not expected if we consider only the supply noise current spectrum since the medium frequency is way below the data rate or the frequencies of internal clock signals. However, it can be easily explained with the power supply network impedance profile. Finally, we correlate the predicted jitter spectrum with the measured jitter spectrum of a serial link operating at 6.4 Gbps.

Jitter modeling in statistical link simulation

Modern high-speed I/O link design requires accurate modeling and simulation of various jitter types including both deterministic and random jitter components. Transient simulators such as SPICE have successfully modeled deterministic jitter but they have limited capabilities to model random jitter. A statistical approach has been recently employed to handle jitter more efficiently. This paper presents a general jitter model suitable for a statistical simulation framework. The proposed model can accurately account for transmitter and receiver random jitter with any distribution and power spectrum density. We have also extended the proposed model to derive a closed-form formula for modeling transmitter clock jitter. The presented methodology is validated using both time-domain simulation and lab measurement.

Prediction of System Performance Based on Component Jitter and Noise Budgets

Conventional ways of summing component specifications to balance voltage and timing budgets are increasingly problematic as data rates continue to scale higher for high speed links. For instance, performance degradation caused by transmitter jitter is more severe than that caused by receiver jitter due to jitter coloring by the passive channel. Furthermore, certain jitter components could interact in the system so it is inaccurate to treat them as independent variables. A system voltage and timing budgeting process hence requires a sophisticated method to accurately predict the overall system performance based on the component specifications. With the recent introduction of a statistical CAD tool, the impact of each individual component, including both deterministic and random jitter, can be co-simulated [l]-[3]. This paper demonstrates the usage of this statistical CAD tool for modeling component budgets. We verify the accuracy of our modeling approach by correlating with a FlexIOreg parallel link interface. Then, we apply the proposed methodology to a PCI Expressreg bus system to estimate the system performance based on published component jitter specification.

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration

The growing demand for low-power and high-fidelity chip-to-chip data communication has motivated the use of near-ground or low-common-mode voltage (LCM) signaling [1-2]. However, deployment of such signaling for high-speed applications such as graphics memory interfaces has been hampered by complications of the transmitter and receiver designs. Recent techniques have enhanced the performance of source-series terminated transmitters by accommodating impedance and equalization calibration at a low power cost [3]. This work advances LCM receiver high-frequency operation by introducing an accurate termination calibration, taking into account the receiver loading on the data link channel. Our receiver also incorporates common-mode-to-differential-gain cancellation and in-situ equalization calibration for reliable data reception at 16Gb/s over a 3” FR4 PCB memory link with 15dB loss at Nyquist frequency.

In-situ characterization of 3D package systems with on-chip measurements

Characterization of I/O channels in 3D package systems is quite challenging as it is difficult to observe signal quality. A traditional way of measuring each device in a component level does not capture complex interaction in 3D integration. Although a sense line can be designed to externally measure noise on power lines, it is not feasible for signal lines as it significantly alters the signal quality. Hence, on-chip measurement features are highly desirable for 3D package systems including emerging Through-Silicon Vias (TSV) technology. In this paper, four key on-chip measurement concepts and circuitries are reviewed: eScope for measuring overall link margins, eWave for capturing a signal waveform, nScope for generating and monitoring on-chip power noise, and zScope for measuring power distribution network (PDN). These circuitries are implemented in a low power differential memory interface. The test vehicle is built based on Package-on-Package (PoP) environment. Measurements from the test vehicle are compared with the predicted data based on simulation.