T. Melly

Design of high-Q varactors for low-power wireless applications using a standard CMOS process

New applications such as wireless integrated network sensors (WINS) require radio-frequency transceivers consuming very little power compared to usual mainstream applications, while still working in the ultra-high-frequency range. For this kind of application, the LC-tank-based local oscillator remains a significant contributor to the overall receiver power consumption. This statement motivates the development of good on-chip varactors available in a standard process. This paper describes and compares the available solutions to realize high-Q, highly tunable varactors in a standard digital CMOS submicrometer process. On this basis, quality factors in excess of 100 at 1 GHz, for a tuning ratio reaching two, have been measured using a 0.5-/spl mu/m process.

An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver

A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility. Their design highlights the tradeoff between performance, lifetime, cost, and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for single battery cell operation). These considerations are illustrated by the design of a prototype receiver chip realized in a standard 0.5-/spl mu/m digital CMOS process with 0.6-V threshold voltage. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit operates at 1-V power supply in the 434-MHz European ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kb/s.

An ultralow-power UHF transceiver integrated in a standard digital CMOS process: transmitter

In the first part of the paper, also in this issue of the JOURNAL, the design of the frequency synthesizer and receiver section of an FSK transceiver was described. It operates in the 434-MHz ISM (Industrial, Scientific, Medical) band and is realized in a standard digital 0.5-/spl mu/m CMOS process. This companion paper focuses on the realization of the transmitter section. It includes a power amplifier, an upconverter, and the circuit generating the baseband quadrature signals with a continuous phase modulation. The overall measured efficiency of the packaged circuit is higher than 38% for a 1.2-V supply and an output power reaching 10 dBm at 433 MHz. The system is designed to still operate at 1-V supply, delivering more than 1 mW with an efficiency higher than 15%.

A low-power low-voltage transceiver architecture suitable for wireless distributed sensors network

A broad range of new high-volume consumer applications require the availability of low-power, battery operated, wireless microsystems. These systems should conciliate a sufficient battery lifetime with reduced overall dimensions (including antenna), low cost and versatility. The design of such systems highlights many tradeoffs between performances, cost and power consumption. These considerations led our group to choose a direct-conversion scheme for a distributed sensors application. The key blocks for this architecture have been realized and measured in a 0.5 /spl mu/m CMOS technology, validating this approach. From these results, the total power consumption of a receiver operating in the 433 MHz ISM band is expected as low as 1.4 mW, under 1.2 V supply, for a sensitivity of -100 dBm and a 20 kbit/s data rate. The transmitter provides 9 dBm output power under the same supply voltage, with a 35% efficiency.

An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers

The sensitivity of RF CMOS receivers using a direct conversion or a low-IF architecture is strongly affected by flicker noise. This paper gives theoretical guidelines to predict the flicker noise in Gilbert-cell mixers. The conversion gain, the equivalent input and output noise, and the effect of the pole at the single internal RF node are discussed. For the first time, results which are valid in all modes of operation are given. Such complete results are required for some ultra low-power and low-voltage applications, since the transistors might be operated in moderate or even weak inversion region. The theoretical gains are found to remain within a 2-dB margin with respect to the measurements of a UHF downconverter built in a 0.5 /spl mu/m process, for a large range of bias conditions and local oscillator swing.

Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process

A broad range of high-volume consumer applications require low-power, battery operated, wireless microsystems and sensors. These systems should reconcile a sufficient battery lifetime with reduced dimensions, low cost and versatility. The design of such systems highlights many tradeoffs between performances, lifetime, cost and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V). These considerations are illustrated by design examples taken from a transceiver chip realized in a standard 0.5 /spl mu/m digital CMOS process. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit prototype operates in the 434 MHz ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kbit/s. The transmitter section is designed for 0 dBm output power under the minimum 1 V supply, with a global efficiency higher than 15%.

A 1 V, 1 mW, 434 MHz FSK receiver fully integrated in a standard digital CMOS process

A broad range of new high-volume consumer applications require the availability of low-power, battery operated, wireless microsystems and sensors. For such applications, a fully integrated receiver based on a direct conversion architecture was designed and realized in a standard 0.5 /spl mu/m digital CMOS process with 0.6 V threshold voltage. It uses FSK modulation in the 434 MHz ISM band, and operates with only 1 V supply, allowing it to be powered by a single battery cell. It achieves a -95 dBm sensitivity for a data rate of 24 kbit/s and an ultralow power consumption of only 1 mW.

A 1.2 V, 430 MHz, 4 dBm power amplifier and a 25 /spl mu/W front-end, using a standard digital CMOS process

Autonomous transceivers working in the ISM UHF bands should meet both requirements of a long battery lifetime and a small overall volume, thus implying a reduction in the receiving power consumption down to less than 1 mW. Ultimately, this goal will only be reached by using original topologies and lowering the supply voltage down to single battery cell operation. A RF front-end and a power-amplifier (PA) designed for the 433 MHz European ISM band are presented. Both RF building blocks have been integrated in a standard 0.5 /spl mu/m digital CMOS process with 0.65 V threshold voltages. The front-end includes an LNA and a downconverter mixer. It achieves a total double sideband (DSB) noise figure of 9 dB, with a dynamic range of 85 dB for a 60 kHz bandwidth, while dissipating only 250 /spl mu/W at 1.2 V supply voltage. The PA includes two fully integrated class A stages together with an output class C amplifier. It achieves a +4 dBm output power with a 15% overall efficiency under 1.2 V supply voltage.

A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]

A low-power and low-voltage (LP/LV) RF front-end operating at 430 MHz and implemented in a standard 0.5 /spl mu/m digital CMOS process is described. Specific LP/LV bias techniques and design tradeoffs are discussed and their application to the design of a fully integrated direct-conversion receiver is presented. The RF building blocks including a 200 /spl mu/A LNA, two different 50 /spl mu/A mixers and a ring-oscillator with differential I-Q outputs consuming 300 /spl mu/A at 430 MHz, have been manufactured and their performances measured. Taking into account the severe power budget, a total double sideband (DSB) noise figure of 17 dB was achieved, together with a spurious free dynamic range of 55 dB at 60 kHz bandwidth, which is sufficient for the targeted application.

A 1.2 V, 433 MHz, 10 dBm, 38% global efficiency FSK transmitter integrated in a standard digital CMOS process

This paper describes the design of an FSK transmitter for the 433 MHz ISM (Industrial, Scientific, Medical) band, which is realized in a standard digital 0.5 /spl mu/m CMOS technology. It includes the PA itself, an upconverter, and the circuit generating the baseband quadrature signals with a continuous phase modulation. The overall measured efficiency of the packaged circuit is higher than 38% for a 1.2 V supply and an output power reaching 10 dBm at 433 MHz.