K. Maeguchi

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

A 54 b*54 b multiplier fabricated in a double-metal 0.5 mu m CMOS technology is described. The 54 b*54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz. >

Temperature dependence of emitter-base reverse stress degradation and its mechanism analyzed by MOS structures

Different degradation modes were observed under high and low reverse stress current conditions. The temperature dependence of the gradation was studied, and it was found that the degradation is greatest around 50 degrees C. The mechanisms of the degradation and its recovery were also investigated, using MOS structures and simulation. MOSFET evaluation indicated that electron trapping and interface state generation occur during the stress. Simulation confirmed that the degradation is caused mainly by the interface states generated in the oxide near the emitter-base junction.<<ETX>>

Analysis of hot-carrier-induced degradation mode on pMOSFET's

Hot-carrier-induced degradation surface-channel (p/sup +/ polysilicon gate) and buried-channel (n/sup +/ polysilicon gate) pMOSFETs is discussed. In the shallow gate bias region, a hot-carrier degradation mode by drain avalanche hot hole injection was found for the surface-channel pMOSFETs. Trapped holes and interface state generation, which were not observed in the buried-channel pMOSFETs, were detected. In this gate bias region, the degradation for the surface-channel structure is smaller than that for the buried-channel structure. Three reasons for the smaller degradation in the surface-channel structure are discussed. The deep-gate bias region was also investigated. In this region, an interface-state generation mode without the threshold-voltage shift was found for both surface- and buried-channel pMOSFETs. This interface state generation is caused by channel hot hole injection. >

A single-chip MPEG2 video decoder LSI

This MPEG2 video decoder LSI decodes MPEG2 standard bit streams. The compression algorithm in the MPEG2 is based on discrete cosine transform (DCT), variable length coding, and motion compensation similar to the MPEG1, the earlier standard. However, the processing speed should be more than four times faster than MPEG1. Moreover, several algorithms and structures to handle interlaced pictures are added to the MPEG1 standard. This LSI decodes in real time all motion-compensation modes and picture structures in MPEG2 bit streams of not only CCIR601 but also HDTV resolution.<<ETX>>

Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's

The analysis indicates that a thinner gate oxide nMOSFET shows smaller degradation. Mechanisms for the smaller degradation were analyzed using a simple degraded MOSFET model. It was found that the number of the generated interface states is defined uniquely by the amount of peak substrate current, independently from the gate-oxide thickness. The major cause of the smaller degradation in the thinner gate-oxide device is smaller mobility degradation due to the generated interface states. The degraded mobility was measured and formulated. The smaller mobility degradation is explained by the difference between the vertical electric field dependence of the Coulomb scattering term and that of the phonon term under the inversion condition. The effect of a larger channel conductance, due to the larger inversion charges for the thinner gate-oxide device, is the secondary cause for the smaller degradation. >

Embedded DRAM technologies

Issues on embedded DRAM technologies including their applications, process options, and tradeoffs are discussed. Real implementations of the embedded DRAM technologies with 0.5 /spl mu/m, 0.35 /spl mu/m, and 0.25 /spl mu/m are also presented. The embedded DRAM technologies will be used to realize high bandwidth and low power operation.

Interface state generation under long-term positive-bias temperature stress for a p/sup +/ poly gate MOS structure

The long-term reliability for a p/sup +/ poly gate MOS structure under low electric field bias temperature (BT) stress is studied. A significant increase in interface-state density was observed for such a structure under positive bias conditions. This phenomenon was not observed in the n/sup +/ poly gate case. The mechanism for this interface-state increase was investigated in detail. Several possible causes, such as mobile ions, excess boron concentration in the gate oxide, electron injection from the substrate, impact ionization in the gate oxide, and hole injection from the gate electrode, were considered. All of the possible causes, except hole injection, were obviated by experiments. Although hole injection current was too small to be detected, hole injection from the p/sup +/ poly gate is a possible cause, which could explain the interface-state generation under positive-bias temperature test. For a p/sup +/ poly gate in CMOS structures, care should be taken when positive bias is applied to the gate electrode. >

Electromigration reliability for a tungsten-filled via hole structure

Experiments have shown that the electromigration reliability for conventional nonfilled via holes decreases with via hole diameter reduction. Tungsten-filled via hole reliability, however, is independent of the via hole diameter and improves significantly compared with the nonfilled via hole structure. The electromigration failure mechanism for the tungsten-filled via hole structures was investigated by two-dimensional numerical simulation. Current crowding points were found near the via hole edge in the aluminum part. Via hole resistance change during the electromigration test was also evaluated. When aluminum-silicon was used for the metal lines, via hole resistance increased, due to the migration of silicon in the aluminum line. However, it was estimated as being negligibly small for unusual operating conditions. >

Increase of resistance to hot carriers in thin oxide MOSFETS

Effects of gate oxide thickness on the hot electron induced degradation in LDD MOSFETs are studied. The device with thinner gate oxide causes less drain current reduction under the same bias stress condition in spite of its highersubstrate current. The relationship between the increase of parasitic drain resistance after stress test and gate oxide thickness shows square dependence. Then the model is proposed to explain that the amount of generated negative charge markedly decrease with decrease of the oxide thickness. And the maximum applicable supply voltage in 0.8µm CMOS with 15nm gate oxide thickness is presumed.

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell

A 4-Mb (512 K words by 8-b) CMOS static RAM (SRAM) with a PMOS thin-film transistor (TFT) has been developed. The RAM can obtain a much larger data-retention margin than a conventional high-resistive load-type well by using the PMOS TFT as a memory cell load. An internal voltage down-converter architecture with an external supply voltage-level sensor not only realizes a highly reliable 0.5- mu m MOS transistor operation but also a sufficiently low standby-power dissipation characteristic for data battery-backup application. A self-aligned equalized level sensing scheme can minimize the sensing delay for a local sense amplifier to drive a large load capacitance of a global sensing bus line. The RAM is fabricated using a 0.5 mu m, triple-poly, and double-aluminum with dual gate-oxide-thickness CMOS process technology. The RAM operates under a single 5-V supply voltage with 23-ns typical address access time and 20- and 70-mA operation current at 10 and 40 MHz, respectively. >