K. Chatty

High-voltage lateral RESURF MOSFETs on 4H-SiC

Owing to high critical electrical breakdown field and large energy gap, SiC has been established as the most promising candidate for high-voltage power semiconductor devices. In the past few years, several high-voltage vertical MOS devices have been demonstrated in SiC, whereas only a 2.6 KV lateral SiC MOSFET has been reported so far. Lateral integrable REduced SURface Field (RESURF) devices are key building blocks for high-voltage power ICs. In this work, we present the first experimental demonstration of a n-channel lateral RESURF MOSFET fabricated on 4H-SiC. The devices exhibit a blocking voltage in excess of 1200 V with a best specific on-resistance of 4 ohm-cm/sup 2/.

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 /spl Omega/-cm/sup 2/. The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability.

Accumulation-layer electron mobility in n-channel 4H-SiC MOSFETs

Accumulation-layer electron mobility in n-channel depletion-mode metal oxide semiconductor field effect transistors (MOSFETs) fabricated in 4H-SiC was investigated using Hall-measurements. The accumulation-layer mobility showed a smooth transition from the bulk value (/spl sim/350 cm/sup 2//V-s) in the depletion regime into accumulation (/spl sim/200 cm/sup 2//V-s). In contrast, the field-effect mobility, extracted from the transconductance, was found to be much lower (/spl sim/27 cm/sup 2//V-s), due to the trapping of the field-induced carriers by interface states. Though the current in depletion/accumulation-mode MOSFETs can be high due to the contribution of bulk conduction resulting in low on-resistance, carrier trapping will cause the transconductance to be low in the accumulation regime.

Hysteresis in transfer characteristics in 4H-SiC depletion/accumulation-mode MOSFETs

Hysteresis in room-temperature transfer characteristics between forward (pinch-off voltage, V/sub P/=-15 V) and reverse gate voltage sweeps (V/sub P/=7 V) in n-channel depletion/accumulation-mode 4H-SiC MOSFETs is reported. Transfer characteristics exhibit a parallel shift toward negative voltages depending,on the starting gate voltage and direction of the sweep. The hysteresis and shift in transfer characteristics are related to changes in effective fixed-oxide charge resulting from changes in interface trap occupancy. Interface trap occupancy changes depending on the magnitude of the starting gate voltage and the direction of gate-voltage sweep. At high temperatures, the hysteresis between forward and reverse gate voltage sweep decreases.