Sauvik Chowdhury

4H-SiC n-Channel Insulated Gate Bipolar Transistors on (0001) and (000-1) Oriented Free-Standing n − Substrates

We experimentally demonstrate 4H-SiC n-channel, planar gate insulated gate bipolar transistors (IGBTs) on 180-μm thick lightly doped free-standing n- substrates with ion-implanted collector regions, and metal-oxide-semiconductor gates on (0001) and (000-1) surfaces. The IGBTs show an ON-state current density of 20 A/cm2 at a power dissipation of 300 W/cm2. The threshold voltages are measured to be 7.5 V and 10.5 V on Si-face and C-face, respectively. Both IGBTs show a small positive temperature coefficient of the forward voltage drop, which is useful for easy parallelization of devices.

1200V, 25A bi-directional Si DMOS IGBT fabricated with fusion wafer bonding

A 1200V, 25A bi-directional silicon DMOS-IGBT has been successfully fabricated using a hydrophobic bonding process at low temperature (400°C). With the aid of a glass carrier approach, a flat and clean bonding surface for producing an electrically stable and transparent junction was achieved. The static and dynamic performance with and without back-side gate control are presented and compared.

Experimental Demonstration of High-Voltage 4H-SiC Bi-Directional IGBTs

We experimentally demonstrate, for the first time, bi-directional 4H-SiC planar gate, insulated gate bipolar transistors fabricated on 250-μm thick, lightly doped free-standing substrates. On Si face, forward voltage drop (at 50 A/cm2) of 9.7 V was obtained at room temperature, with a differential ON-resistance of 140 mQ · cm2, indicating good conductivity modulation. We have also demonstrated control over minority carrier injection in static characteristics of the BD-IGBTs by application of a back-gate bias.

Characteristics of 4H-SiC P-i-N diodes on lightly doped free-standing substrates

This paper presents static and dynamic electrical characteristics of implanted 4H-SiC PiN diodes fabricated on Si-face and C-face of lightly doped free-standing substrates. The device performance is found to be comparable to conventional diodes. Carrier lifetime of about 2.5 μs was measured for the drift region.

Comparison of 600V Si, SiC and GaN Power Devices

In this paper the DC and switching performance of 600V Si, SiC and GaN power devices using device simulation. The devices compared are Si superjunction MOSFET, Si field stop IGBT, SiC UMOSFET and GaN HEMT.

Characteristics of MOS Capacitors with NO and POCl3 Annealed Gate Oxides on (0001), (11-20) and (000-1) 4H-SiC

MOS capacitors have been fabricated on (0001), (11-20) and (000-1) oriented 4H-SiC under different post-oxidation anneal (POA) conditions. 100 MHz conductance measurement shows the generation of very fast donor-type interface traps after NO anneal for both Si-face (0001) and a-face (11-20), but not on C-face (000-1). Fast traps were not observed in POCl3 annealed samples for any orientation. Smallest Dit (at 0.2 eV below conduction band edge) was obtained on Si-face using POCl3 anneal (1.4x1011 cm-2 eV-1), on a-face using NO anneal (2.5x1011 cm-2 eV-1) and on C-face using POCl3 anneal (4.5x1012 cm-2 eV-1).

Fabrication of thick free-standing lightly-doped n-type 4H-SiC wafers

In this work, we have developed a selective wet etching technique for n+-SiC substrate using electrochemical etch process. A mixture of hydrofluoric acid and hydrogen peroxide was used as an electrolyte and the etch rates exceeding 200 μm per hour at the current density of 50 mAcm-2 was achieved. This process is highly selective and the etching process stops at the interface of n+ SiC substrate and n-SiC epi layer. Using this process, we have successfully fabricated 180 to 250 μm thick 4’’ n-SiC epitaxial free standing wafers by separating them from a 350 μm thick n+ SiC substrate. After the substrate is completely removed, free standing wafer is characterized for wafer bow and minority carrier lifetime, using both Si-face and C-face. The wafer bow was reduced from 40 μm to 20 μm after the substrate removal. It was found that the process of removing the substrate does not introduce any extra damage to the wafer as far as the lifetime is concerned. The hole lifetime measured by microwave photoconductivity decay technique was unchanged at around 2 μsec, measured from both Si-face and C-face. These results are very promising and open up many avenues for many device applications where lightly doped free standing epitaxial semiconductor thin film is needed.

Effect of Activation Annealing and Reactive Ion Etching on MOS Channel Properties of (11-20) Oriented 4H-SiC

In this paper we have investigated the effect of two key processing steps for the fabrication of 4H-SiC trench gate power MOSFETs, namely activation annealing and reactive ion etching on the MOS interface properties of a-face (11-20) 4H-SiC. By optimizing activation annealing conditions, high channel mobility (µfe) of 111 cm2/V.s, threshold voltage (VT) of 3.5V and subthreshold slope (S) of 194 mV/dec was obtained. However, after reactive ion etching (RIE) of the surface, µfe reduced to 81 cm2/V.s with increase in VT to 5V and S to 331 mV/dec. This is possibly due to increase in interface trap density from 1.8×1012 cm-2 to 3.3×1012 cm-2 after RIE treatment estimated from by MOS gated diode characteristics. Increased trap density contributes to higher coulombic scattering as indicated by the weaker temperature dependence of high field mobility in RIE etched sample.

Study of Mobility Limiting Mechanisms in (11-20) 4H-SiC NO Annealed MOSFETs

NO annealed Lateral (11-20) MOSFETs were fabricated and mobility limiting mechanisms were investigated by MOS-gated Hall measurements, impedance analysis of MOS capacitor and so on. We have clarified that about 1×1012 cm-2 of inversion electrons are trapped at the interface and mobility is largely limited by Coulombic scattering. We attribute that the Coulombic scattering is caused by electrons trapped at interface states and positive fixed charges, which might be due to donor-like states.

3300V SiC DMOSFETs Fabricated in High-Volume 150 mm CMOS Fab

We fabricated 3300V Silicon Carbide (SiC) DMOSFETs on 150mm substrates in a high volume automotive qualified Si CMOS foundry. In this paper we will show that JFET optimization can yield noticeable improvements in on-state performance without exceeding acceptable gate oxide electric fields. For the optimized design, breakdown voltages (BV) in excess of 3900V are observed along with a specific on resistance of 13.5mOhm-cm2 at room temperature and 30mOhm-cm2 at 150°C.