T.S. Cale

Wafer-Level Three-Dimensional Hyper-Integration Technology Using Dielectric Adhesive Wafer Bonding

A viable wafer-level 3D hyper-integration technology platform with dielectric adhesive bonding and copper vias has been described. An inter-wafer via-chain structure has been fabricated, demonstrating the feasibility of this 3D technology, with a baseline process flow of one-micron wafer-to-wafer alignment, BCB wafer bonding, three-step wafer thinning and copper damascene patterned inter-wafer interconnection. Evaluations indicate the thermal, mechanical, and electrical robustness of the baseline wafer bonding and thinning processes as well as compatibility with BEoL processes and packaging. The key advantages of BCB wafer bonding include the ability to accommodate wafer-level non-planarity (e.g., surface topography, wafer bow) and particulates at the bonding interfaces, high bond strength, and relatively low temperature bonding process as well as high temperature stability after bonding.

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

Monolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Wafer Thinning for Monolithic 3D Integration

A three-step baseline process for thinning of bonded wafers for applications in threedimensional (3D) integration is presented. The Si substrate of top bonded wafer is uniformly thinned to ~35 μm by backside grinding and polishing, followed by wet-etching using TMAH. No visible changes at the bonding interface and damage-free interconnect structures are observed after the thinning process. Both mechanical and electrical integrity of the bonded pairs are maintained after the three-step baseline thinning process, with electrical tests on wafers with multi-level copper interconnect test structures showing only a slight change after bonding and thinning. This thinning process works well for Si removal to an etch-stop layer, although present process uniformity is not adequate to thin bulk Si substrates. Other issues such as wafer breakage and edge chipping during Si thinning and their possible solutions are also addressed.

Hybrid Grain-Continuum Model for Thermo-Mechanical Stresses in Polycrystalline Cu 3D IC Vias

We introduce an approach to compute stresses in structures in which grain structures are important. The approach is a hybrid of continuum representations and 3D grain-continuum (GC) models; i.e., models in which grain boundaries are represented and tracked. Stresses due to temperature changes in 3D IC vias are used as to demonstrate our approach. We focus on determining how large the GC region needs to be; that is, how much the computations can be simplified.