T. Schram

Electrical and Material Evaluation of the MOCVD TiN as Metal Gate Electrode for Advanced CMOS Technology

The electrical and material characterization of Ti(C)N deposited by metal organic chemical vapor deposition (MOCVD) technique, as metal gate electrode for advanced CMOS technology is investigated. The effects of the plasma treatment, post anneal treatment and the thickness variation of the Ti(C)N film on the flat band voltage (VFB) and effective work function (WF) of the Poly-Si/Ti(C)N/SiO 2 Poly-Si/Ti(C)N/SiO 2 gate stack s are reported. We found that both the in-situ plasma treatment and post anneal treatment help in reducing the carbon content (organic) in the film making it more metallic compared to the as-deposited films. However, the post anneal treatment was found to be a better option for getting rid of hydrocarbons as compared to plasma treatment from the gate dielectric integrity point of view. The thickness variation of post annealed Ti(C)N film ranged from 2.5 nm to 10 nm lead to WF shift of upto ~350 mV for both Poly-Si/Ti(C)N/SiO 2 and Poly-Si/Ti(C)N/HfO 2 gate stacks.

Multiple-Vt FinFET devices through La 2 O 3 dielectric capping

In this work, the possibility of achieving low Vt nMOS FinFET transistors through the use of a La₂O₃ dielectric cap, and the ability of co-integrating La₂O₃ capping with medium and low Vt pFinFET devices are investigated. A significant improvement in device performance was shown for thin La₂O₃ capping with CVD TaN electrode.

Implementation of high-k gate dielectrics - a status update

The authors discuss Hf-Al mixed oxide characteristics, and applications to MOS capacitors and transistors. XRD an TEM analyses are performed and crystallisation behaviour analysed.

Defect Profiling and the Role of Nitrogen in Lanthanum Oxide-capped High-κ Dielectrics for nMOS Applications

Results from an extensive reliability characterisation of Lanthanum oxide-capped HfSiO(N) devices are reported for the first time. It is shown that the effect of nitrogen presence in the high-κ is significant; whereby the ability of lanthanum oxide to interact with the high-κ dielectric is reduced, with detrimental consequences on device reliability. A profile of defects in the gate stack is proposed, inferred from a combination of reliability measurements. Introduction The quest to achieve band edge effective workfunction values for sub 32 nm CMOS devices looks unlikely to be resolved solely by choice of electrode on a single high-κ dielectric layer. It is becoming more evident that an additional dielectric layer will be required to tune the threshold voltage/effective workfunction. To date, rare earth capping layers have been reported to effectively reduce the threshold voltage on nMOS devices, where up to 500 mV Vt tuning can be achieved, depending on the La2O3 cap/high-κ combination [1-3]. However, to date no extensive reliability characterisation of these capped dielectrics has been reported, in terms of defect profiling in the stack resulting from various analysis techniques. This provides the aim of this work, using gate/dielectric stacks with promising Vt/eWF characteristics. Experimental nMOS devices were fabricated with 1.0 nm chemical oxide starting surface. 2.9 nm (unless specified) MOCVD HfSiO was deposited and was subsequently nitrided by a plasma process. 0-1.0 nm ALD La2O3 cap layers were deposited, before sputtering TaN electrodes, junction activation annealing at 1030C, and forming gas annealing. Results Using TaN as the gate electrode presents thermodynamically stable (although midgap) material, which when combined with a 1.0 nm La2O3 cap, results in Vfb/Vt tuning capabilities up to 270 mV (Figure 1). From the inset, it is clear the Vt values reduce with increasing cap layer thickness, and also the gm peak values decrease. There is no significant change in the interface state density as evaluated from base level charge pumping (Figure 2), suggesting the transconductance/ mobility reduction is related to a presence of bulk charge. PBTI analysis on the capped and reference sample indicate enhanced electron trapping in the capped film relative to the reference (Figure 3). The 10 year operating voltage (for 30 mV ΔVt) reduces from 1.33V for the uncapped film to 1.01V for the 1.0nm cap case. The degradation under hot carrier stressing is shown in Figure 4 to be higher for the capped film (where the 10 year lifetime is reached at 1.84V, compared to 1.92 V for the uncapped reference). Hysteresis in Id-Vg traces indicate increased electron trapping with cap thickness (Figure 5), both at the Si/SiO2 interface (deduced from the slight transconductance peak degradation during hysteresis measurement [4]) and predominantly deeper in the stack (from threshold voltage shift in Figure 5 [5]). TDDB lifetime of the devices increases with the thickness of the cap layer (Figure 6), from 1.03 V to 1.15 V for the uncapped and 1.0 nm capped films, respectively, which is believed to result from the increased physical thickness of the dielectric layers, as evidenced in the difference in inversion capacitance (Figure 1). To summarise the results of the TaN/1.0 nm La2O3/2.9 nm HfSiON stacks, it is shown that a strong Vt reduction is achieved, however this is achieved at a cost to the reliability. As the CET of these films is higher than that targeted, a further study was performed on thinner dielectrics. Given the negative effects of lanthanum incorporation on reliability, both the high-κ and cap layer thickness were scaled down (to 1.8 nm and 0.7 nm, respectively) in a bid to reduce the thickness of the stacks. An uncapped reference was also examined. No nitridation was performed on the dielectric, which were deposited on n and pMOS samples. The effect of this is a 380 mV Vt reduction with 0.7 nm La2O3 layer incorporation, at 1.6 nm CET. The BTI characteristics are presented in Figure 7, where the 10 year lifetime is achieved for reference and capped films at gate overdrive values of 0.79V and 0.92 V, respectively after PBTI stress. Interestingly the lifetime is increased by the presence of the cap. NBTI analysis of the La2O3 capped devices demonstrates a reduced lifetime with cap layer. The peak transconductance degradation during NBTI stressing is enhanced for the capped layer (not shown), which indicates an increase in interface state generation [4]. The degradation under hot carrier stressing is shown in Figure 8, where the 10 year lifetime is reached at Vds = 1.92 V with cap, and 1.94 V for the uncapped reference. The current-time traces during substrate (Vg>0, Figure 9) and gate (Vg<0, Figure 10) injection are shown for reference and capped films to help explain these results. From substrate injection, the fast initial transient for the capped film is consistent with electron trapping in the high-κ, as detected in PBTI and Id-Vg (see below). From gate injection, the initial transient suggests enhanced electron trapping in the SiO2 interface layer, which could explain the hot carrier degradation for the capped film (Figure 8). TDDB results are presented in Figure 11, and it is seen an increased 10 year operating voltage is obtained with the cap (1.07 V compared to 0.90 V for no cap). The beta values increase from 1.05 for the uncapped film, to 1.49 for the capped (also seen for La2O3 capped pMOS devices (not shown)), suggesting a difference in the defect creation mechanism throughout the stack. This is further proof of a significant interaction between the cap layer and the host dielectric. From repeat Id-Vg sweeps on nMOS and pMOS devices in Figure 12, slight (positive) hysteresis is seen on the nMOS capped layer. Defect distribution and the role played of nitrogen There is a significant difference in the reliability characteristics of the two series of gate stacks examined in this work. Adding 1.0 nm La2O3 to 2.9 nm HfSiON results in a deterioration of reliability characteristics, whereas adding 0.7 nm La2O3 to 1.8 nm HfSiO enhances the reliability. As only the first sample set received a nitridation step, this is believed to result in an increased thermodynamic stability [6], whereby interaction between La2O3 and HfSiON/SiO2 is less than that between La2O3 and HfSiO/SiO2. This agrees with the cap induced effects observed, notably (1) a higher Vt shift (Figures 12 & 5) and (2) the significant TDDB-beta value increase for the non-nitrided stack (Figures 11 & 6). Combining these results can lead to a defect profile in the band gap as shown in the inset of Figure 12. Defects are seen at the Si/SiO2 interface ([A] E>Ei from Δgm peak during Id-Vg hysteresis/HCS (with higher density for the non-nitrided film), [B] E<Ei from NBTI), and in the high-κ layer ([C] close to the MG/hi-κ interface; from voltage dependence of PBTI and evolution of I-t traces, and [D] close to the SiO2/hi-κ, from NBTI). The convergence of PBTI degradation for capped and uncapped films (Figure 7B) with reducing stress conditions suggests the dominant defects in the capped films are at an energy level whereby they will not be accessed during device operation. The defects in the interface layer of the non-nitrided film, accessed during HCS measurements (Figure 8) do not radically shift the lifetime, suggesting a relatively low density, which again is promising from a reliability perspective. Coupled with the Vt-tuning potential of these layers, they provide a promising reliable route for future generation CMOS scaling. Conclusions This work provides an extensive reliability characterisation of dielectric stacks for the 32 nm node, which incorporate rare earth (lanthanum) oxide capping layers. It is shown that the effect of nitrogen incorporation is significant on the reliability of lanthanum oxide containing devices. A defect distribution is proposed throughout the gate stack to explain the results observed. Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba, 2008,

RMG Patterning by Digital Wet Etching of Polycrystalline Metal Films

A self-limiting wet etching of metal thin films has been developed for the replacement metal gate patterning in advanced logic devices, which will have aggressively scaled gate length and fin pitches. A uniform and highly selective wet etching of polycrystalline TiN films is demonstrated by a diffusion-limiting oxide growth on the metal surfaces as well as a subsequent highly selective oxide removal.

Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme

RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme A. Veloso, G. Boccardi, L.-Å. Ragnarsson, Y. Higuchi, H. Arimura, J. W. Lee, E. Simoen, M. J. Cho, Ph. J. Roussel, V. Paraschiv, X. Shi, T. Schram, S. A. Chew, S. Brus, A. Dangol, E. Vecchio, F. Sebaai, K. Kellens, N. Heylen, K. Devriendt, H. Dekkers, A. Van Ammel, T. Witters, T. Conard, I. Vaesen, O. Richard, H. Bender, R. Athimulam, T. Chiarella, A. Thean, and N. Horiguchi Imec, assignee at Imec from Panasonic, Kapeldreef 75, 3001 Leuven, Belgium; also at K. U. Leuven, Belgium Tel.: +32-16-28 17 28, Fax: +32-16-28 17 06, Email: Anabela.Veloso@imec.be

Effective Work Function Engineering for Aggressively Scaled Planar and FinFET-based Devices with High-k Last Replacement Metal Gate Tech.

Devices with High-k Last Replacement Metal Gate Technology A. Veloso, S. A. Chew, Y. Higuchi, L.-Å. Ragnarsson, E. Simoen, T. Schram, T. Witters, A. Van Ammel, H. Dekkers, H. Tielens, K. Devriendt, N. Heylen, F. Sebaai, S. Brus, P. Favia, J. Geypen, H. Bender, A. Phatak, M. S. Chen, X. Lu, S. Ganguli, Y. Lei, W. Tang, X. Fu, S. Gandikota, A. Noori, A. Brand, N. Yoshida, A. Thean, and N. Horiguchi IMEC, assignee at IMEC from Panasonic, Applied Materials Belgium NV, Kapeldreef 75, 3001 Leuven, Belgium; Applied Materials Inc., 3050 Bowers Ave., Santa Clara, CA 95054, USA Tel.: +32-16-28 17 28, Fax: +32-16-28 17 06, Email: Anabela.Veloso@imec.be

Wafer backside cleaning strategies for high-k/metal gate processing

In this work the removal of different metallic and particulate contaminants relevant for high-k/metal gate processing is studied. Best cleaning efficiency of both silicon and nitride substrates is achieved using a HF/HNO3-based cleaning resulting in a particle removal efficiency higher than 90% and metal removal down to 1010 at/cm2.