A. Van Ammel

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.

Highly scalable bulk FinFET Devices with Multi-V T options by conductive metal gate stack tuning for the 10-nm node and beyond

A scalable multi-VT enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-VT is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ~400 mV is realized by adjusting the TiN bottom barrier thickness underneath TiAl, while over 200 mV shifts are achieved by means of implantation of nitrogen into ALD TiN/TiAl/TiN. The gate-stack Tinv, JG, DIT and reliability as well as the device performance are shown to be unaffected by the multi VT process.

Evidence of the Influence of Heavy-doping Induced Bandgap Narrowing on the Collector Current of Strained SiGe-base Heterojunction Bipolar Transistors

Based on an analytical approach, developed by Jain and Roulston [1], the different contributions to the bandgap narrowing at T=0K are calculated for highly p-type doped Si and strained Si<inf>1-x</inf>Ge<inf>x</inf> layers for Ge-concentrations between 0 and 30%. The different assumptions will be highlighted with special emphasis on the procedure we used to deal with the non-parabolic aspect of the valence band. This result will be used to calculate the apparent bandgap narrowing in these layers. These theoretical results will then be compared to the experimental results obtained on mesa-type Heterojunction Bipolar Transistors with strained Si<inf>1-x</inf>Ge<inf>x</inf>-base and poly-emitter. The Ge-concentration in these layers was between 0 and 16% while the B-doping was varied between 5.10¹⁷/cm³ and 5.10¹⁸/cm³.

Process control & integration options of RMG technology for aggressively scaled devices

We report on aggressively scaled RMG-HKL devices, with tight low-V_T distributions [σ(V_Tsat) ~ 29mV (PMOS), ~ 49mV (NMOS) at L_gate~35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen sources reduction, control of RF-PVD TiAl/TiN ratio and reduced H_gate, also impacting stress induced in the channel. Additional key features: 1) Al vs. W as fill-metal, with careful liner/barrier materials selection and tuning yielding well-behaved devices with tight R_gate distributions down to L_gate~20nm, and enabling both PMOS and NMOS low-VT values for high aspect-ratio gates (H_gate~60nm, L_gate≥30nm); 2) wet-etch vs. siconi clean for dummy-dielectric removal, with HfO₂ post-deposition N₂-anneal resulting in substantial BTI improvement without EOT or low-field/peak mobility penalty, and good noise response.

Low temperature selective growth of epitaxial Si and Si1−xGex layers from SiH4 and GeH4 in an ultrahigh vacuum, very low pressure chemical vapour deposition reactor: kinetics and possibilities

Abstract The kinetics of the growth of epitaxial and polycrystalline undoped and heavily p-type-doped Si and Si 1− x Ge x layers have been studied over the pressure range from 4×10 −4 to 1.5 Torr at 625°C in an ultrahigh vacuum chemical vapour deposition reactor by growing layers for various times and measuring the resulting thicknesses. The pressure influence on the epitaxial as well as on the polycrystalline Si growth rate is discussed. We observed that nucleation of Si on Si as well as on SiO 2 is retarded. A model is proposed which explains this incubation time for the nucleation of Si on Si and the influence of the pressure on it. The addition of GeH 4 to the SiH 4 growth environment is found to retard the nucleation on SiO 2 even longer. On the other hand, a pressure increase and the addition of B 2 H 6 accelerate nucleation. Epitaxial layers can be grown selectively on Si by limiting the growth period to below the incubation time of polycrystalline material. Maximum selective thicknesses for various types and combinations of layers have been determined.

Preparation of hydrogenated amorphous-silicon with tunable gap by homogeneous chemical vapor-deposition

This paper reports on the properties of doped and undoped amorphous silicon films deposited by the homogeneous chemical vapor deposition (HOMOCVD) technique. It is shown that good quality films can be grown at reasonable deposition rates of 100–150 A/min. It is also shown that in this growth regime, the main precursor is Si2H4, shifting to SiH2 at higher H2 dilution. The real limit for the growth rate is set by the phenomena of homogeneous and local nucleation. The optical band gap of undoped films deposited at these high growth rates, changes from 2.6 eV for a substrate temperature of 20 °C down to 1.6 eV at 280 °C. Very conductive B‐doped HOMOCVD amorphous silicon films with tunable band gap can be obtained. This is very important for the use of such films for window layers in photovoltaic applications as an alternative to siliconcarbide. At a substrate temperature of 40 °C films were obtained with an optical gap of 2.34 eV and a room‐temperature dark conductivity of 1.6×10−5/Ω cm. Down to a thickness o...

On the relation between low-temperature epitaxial growth conditions and the surface morphology of epitaxial Si and Si1−xGex layers, grown in an ultrahigh vacuum, very low pressure chemical vapour deposition reactor

Abstract In this paper we describe the intimate relation between the surface morphology of epitaxial Si and Si1−xGex layers and the pressure during growth. All the experiments were done at a temperature of 625 °C and the pressure was varied between 10−4 and 2×10−1 Torr. The layers were grown in an ultrahigh vacuum very low pressure chemical vapour deposition reactor (UHV-VLPCVD) with a gas mixture of SiH4 and GeH4 without the addition of H2. Based on the pressure and the growth-initiating conditions, we distinguish two different growth modes, based on a different surface morphology and growth rate. The first mode (mode I) is characterized by a high growth rate and good surface morphology, whereas in mode II the growth rate is significantly lower and the surface morphology substantially rougher. We present also a qualitative explanation for these observations in terms of hydrogen coverage and impingement rate of precursor molecules on the growing crystal surface.

Influences of trace metal impurities on the thermal quenching of photoluminescence in hydrogenated amorphous silicon by homogeneous chemical vapor deposition

The influence of trace metal impurities of low‐temperature undoped amorphous silicon by homogeneous chemical vapor deposited a‐Si:H has been explored for the first time. The metal impurities Ni, Cr, and Fe cause a shift of the transition temperature for the double‐activated regime to a relatively low value. However, Ga and B impurities quench the photoluminescence intensity at a low temperature. Both of them cause weak photoemission of the films at room temperature. The shift of the transition temperature can be explained by the presence of non‐radiative deep recombination centers. The quenching of the photoluminescence intensity is caused by the presence of nonradiative recombination centers.

Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme

RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme A. Veloso, G. Boccardi, L.-Å. Ragnarsson, Y. Higuchi, H. Arimura, J. W. Lee, E. Simoen, M. J. Cho, Ph. J. Roussel, V. Paraschiv, X. Shi, T. Schram, S. A. Chew, S. Brus, A. Dangol, E. Vecchio, F. Sebaai, K. Kellens, N. Heylen, K. Devriendt, H. Dekkers, A. Van Ammel, T. Witters, T. Conard, I. Vaesen, O. Richard, H. Bender, R. Athimulam, T. Chiarella, A. Thean, and N. Horiguchi Imec, assignee at Imec from Panasonic, Kapeldreef 75, 3001 Leuven, Belgium; also at K. U. Leuven, Belgium Tel.: +32-16-28 17 28, Fax: +32-16-28 17 06, Email: Anabela.Veloso@imec.be

Materials and thermal stability of tantalum carbide layers for metal gate applications

Phase compositions and thermal stability of different TaC_x layers deposited by PVD is studied using in-situ high-temperature XRD (HT-XRD). It is found that the phase composition of the as-dep. layers and those during annealing at high temperatures strongly depends on their chemical compositions. Low carbon layers (~Ta₄C) are amorphous below 700degC, and crystallize into hexagonal Ta₂C in 700-900degC. At 1150degC, the Ta₂C is replaced by TaSi₂. Stoichiometric Ta₂C are also dominantly amorphous below 900degC and starts to form cubic TaC at 900degC, and TaSi₂ at 1100degC. The as-dep. TaC layers are crystalline, with a dominant cubic TaC phase. At 1000degC, the TaC is replaced by TaSi₂