Y. Momiyama

V/sub th/ fluctuation induced by statistical variation of pocket dopant profile

This paper studies effect of pocket (halo) profile on V/sub th/ fluctuation due to statistical dopant variation by measurement and simulation. A pocket profile significantly enhances V/sub th/ fluctuation by a factor of >15% at worst even if the implantation process variations would be negligible. This is because pocket dopants shrink the area which controls V/sub th/.

A high performance 50 nm PMOSFET using decaborane (B/sub 10/H/sub 14/) ion implantation and 2-step activation annealing process

A high performance 50 nm PMOSFET with 7-nm-deep ultra shallow junction is described. Ultra-low energy implantation of B/sub 10/H(14/sup +/) at 2 keV (effective energy of boron is 0.2 keV) which never causes transient enhanced diffusion (TED) is utilized for the extension formation. To prevent thermal diffusion (TD), we developed a 2-step activation annealing process (2-step AAP) which forms a shallow extension with a low temperature annealing after the deep source/drain (S/D) formation. The highest drive current of 0.40 mA/um (@I/sub off/ of 1 nA/um and V/sub d/=-1.8 V) which improves 15% as compared with published data is achieved. The smallest PMOSFET with a L/sub eff/ of 38 nm is demonstrated for the first time. A low S/D series resistance R/sub sd/ of 760 ohm-um is achieved even if using a high sheet resistance (>20 Kohm/sq) for the extension regions due to the diminished extension length.

Fmax enhancement of dynamic threshold-voltage MOSFET (DTMOS) under ultra-low supply voltage

The high frequency characteristics of DTMOS are described here for the first time. Our DTMOS has a small parasitic resistance due to an optimized Co salicide technology and a small parasitic capacitance due to a reduction in the overlapped region between the gate and drain, which is achieved by gate poly-Si oxidation before LDD implantation. We obtained an Ft of 78 GHz and an Fmax of 3.7 GHz for a 0.1-/spl mu/m-Leff DTMOS even at a supply voltage of 0.7 V. We also noted an Fmax enhancement of 1.5 times compared to that of a conventional SOI MOSFET, which is attributed to a high transconductance and a large output resistance.

Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs

In this paper, the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-MOSFETs was directly evaluated. Using scanning tunneling microscopy (STM), it was clearly observed that the roughness of extension edges induced by gate LER strongly depended on the implanted dose, pockets, and coimplantations. Impurity diffusion suppressed by a nitrogen (N) coimplant enhanced the roughness of the extension edges, which caused fluctuations in the device performance. The expected effect based on the carrier profiles measured by STM of the N coimplant on the electrical performance of the n-MOSFETs was verified

A 140 GHz ft and 60 GHz fmax DTMOS integrated with high-performance SOI logic technology

We integrated an RF-nMOSFET with 130-nm SOI high-end logic technology. Using the dynamic threshold structure (DTMOS) and channel engineering, we obtained an ft of 140 GHz and an fmax of 60 GHz when Vgs=0.65 V and Vds=1.5 V, while the logic CMOS showed Ion-Ioff characteristics better than those reported for SOI-CMOS devices. The RF characteristics were analyzed using a newly developed small-signal equivalent circuit model that has an additional current source to express the body contribution of the DTMOS. These analyses revealed that channel engineering is important in improving RF performances.

Direct measurement of effects of shallow-trench isolation on carrier profiles in sub-50 nm N-MOSFETs

The effects of shallow-trench isolation (STI) on the carrier profile of the extension region in sub-50-nm n-MOSFET were directly measured for the first time. The extension overlap length drastically decreased by 3 run within a distance from STI (Y) of 50 nm. In contrast, the channel concentration gradually increased within Y of 100 nm. The STI effect was also measured for transistors with a gate width of less than 130 nm in 6T-SRAM cell. Reduction of the STI effect by nitrogen co-implant suppressed sub-threshold leakage current by up to an order of magnitude and decreased fluctuation in the threshold voltage by 8 %.

Direct evaluation of gate line edge roughness impact on extension profiles in sub-50nm N-MOSFETs

We directly evaluated the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-FETs. Using scanning tunneling microscopy, we clearly observed that the roughness of the extension edges induced by the gate LER strongly depended on the implanted dose, pockets, and co-implantations. Impurity diffusion suppressed by a nitrogen (N) co-implant enhanced the roughness of the extension edges, which caused fluctuation in the device performance. We verified the expected impact of the N co-implant on the electrical performance of the n-FETs.

High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

Aggressively scaled 25 nm gate CMOSFETs for the 65 nm node are reported. We successfully improved the short channel effect while keeping a high drive current by using total process controls (SW, offset-spacer, extension, halo, mechanical stress, etc.). Both mobility in nMOS and NBTI in pMOS are improved by combination of low temperature annealing and oxynitride gate oxide with low nitrogen concentration. High drive currents of 840/1010 /spl mu/A//spl mu/m and CV/I values of 0.54/0.60 psec with 25/33 nm gate nMOSFETs were achieved at Vdd=1 V and Ioff=100 nA//spl mu/m. They are the best values among recent published papers.

A 185 GHz f/sub max/ SOI DTMOS with a new metallic overlay-gate for low-power RF applications

The dynamic threshold MOS transistor (DTMOS) built on an SOI substrate is one candidate to realize low-power one-chip RF and high-speed digital integrated circuits for wireless communication systems and optical fiber links. Scaling down the characteristic length of the DTMOS is aggressively performed, and the cut-off frequency (f/sub T/) has been drastically increased. Although the f/sub T/ is steeply rising every year, improvement of the maximum oscillation frequency (f/sub max/) is very slow. This is due to a limitation of the silicide based gate resistance (Rg) in the conventional logic CMOS process. Many interesting ways with optimized layout such as folded gate finger and multi-finger pattern have been proposed, and great efforts to make Rg small have been made. The most effective way to perform further reduction of Rg is to use a low resistive metal-gate or a metallic overlay-gate that is fabricated on the poly-Si fine gate. In this paper, we propose an 80 nm gate SOI-nDTMOS with a new gate structure. The key is to introduce a metallic overlay-gate process into the conventional logic CMOS fabrication process. Using the metallic overlay-gate structure, we achieved the f/sub max/ of 185 GHz at low bias voltage, which is, in our knowledge, the world record ever reported for Si MOSFETs.

Suppression of Poly-Gate-Induced Fluctuations in Carrier Profiles of Sub-50nm MOSFETs

We have investigated what effects randomly oriented and rotated poly-Si gate grains have on lateral carrier profiles in sub-50-nm MOSFETs by direct observations and electrical measurements. Since amorphous gates suppress random channeling penetration of pocket implants, we have increased effective mobility (40%), improved Vth roll-off characteristic (7 nm) and decreased Vth fluctuation (-26%)