Kazuyuki Maruo

A small-area high-performance 512-point 2-dimensional FFT single-chip processor

A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource saving multi-datapath radix-2/sup 2/ computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2-dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.8 /spl times/ 2.8 mm/sup 2/ with CMOS 0.35 /spl mu/m triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensional FFT in 23.2 /spl mu/sec and a 2-dimensional one in only 23.8 msec at 133 MHz operation.

An image recognition processor using dynamically reconfigurable ALU

An image recognition processor, utilizing a phase only correlation (POC) algorithm is proposed. The arithmetic logical unit (ALU) in this processor can be re-configured dynamically. By arranging the POC algorithm to a form suitable for reconfigurable computing, the proposed processor can perform 2D 512/spl times/512 pixel image recognition within 105.2 ms and using 310.9 mW of power. This power consumption is 11.3 times lower than that of a previously reported work with same execution time.

A dynamically-reconfigurable image recognition processor

Summary form only given. We introduce a new image recognition processor using a run-time reconfiguration (RTR) technology. A phase impulse response function (PIRF) is employed as an application for evaluating the performance of RTR architecture. By utilizing the RTR architecture effectively, a complicated image processing application such as PIRF can be implemented on a single processor. To achieve this, a dynamically-reconfigurable arithmetic logic unit (DRALU) is proposed. Simulation results show that our proposed processor using DRALU can execute the PIRF within 30 msec.