Tadao Komeda

A Low Power 8 Bit Parallel A/D Converter with High Accuracy Process

A high accuracy process offering small ΔVBE of pair transistors, small contact resistance, and uniform reference resistance, has been applied in the design of an 8 bit parallel 40 MHz A/D converter. A new bipolar structure produced by serial implantation of B+ and Ass+ through the same opening window of SiO2 has been developed to realize high speed and high uniformity. An optimized high speed comparator stage was developed in which the number of transistors and power consumption were reduced. Consequently, an 800 mW, 40 MHz sampling frequency, 8 bit A/D converter was developed.

Flat Emitter Transistor with Self-Aligned Base

A flat emitter transistor with a self-aligned base (FLET) has been developed to realize a high speed and low power dissipation bipolar LSI. This FLET has a flat bottom emitter and eliminates parasitic capacitance in the side wall. Accordingly, current gain (hFE) is almost independent of the emitter size and shape. Moreover, high cut-off frequency (fT) and high hFE can be obtained in low current region. The FLET also has an inactive base of high impurity density formed extremely near the emitter region. As a result, the base resistance can be lowered even though single line base structure is used. This base contact structure enables the reduction of CTC and CTS. The divider using FLET operated at frequencies up to 1.3 GHz. The power dissipation was 125 mW, being one fifth that of the conventional divider.