Toyoki Takemoto

New SOI CMOS process with selective oxidation

Both NMOSand PMOS-transistors have been fabricated on the silicon islands based on the conventional polysilicon-gate CMOS process technique (Fig. 4). Subthreshold leakage current for the W/L = 1.5pd0.8pm n-channel transistor is less than O.lpA (Fig. 5-a). Transistors fabricated on poorly planarized structures show a hump in an Id-Vg curve (Fig. 5-b), that is ascribable to the threshold lowering at the MOSFET channel edge3). Effective inversion mobility of electrons is about 600cm2/Vsec and that of holes is about 300cm2/Vsec. These values are comparable with those of bulk CMOS transistors. Both 25-stage CMOS ring oscillators and 1/2 frequency dividers can successfully be fabricated, and their excellent characteristics are confirmed. Each stage comprises NMOSand PMOS-transistors with same size of W/Leff = 1.5!,1m/1.3pm. The delay time per stage at Vdd = 5 V is 360 psec with 0.033pJ per stage power dissipation.

Interferometric Nanometer Alignment for a Wafer Stepper by Two Wave-Front Reconstruction onto Deformed Wafer Gratings

A discussion is presented on a reduction projection wafer stepper with an interferometric nanometer alignment detector by two wave-front reconstruction. The optics of the detector to form an interferometer comprises two coherent beams and a grating on a wafer. The alignment detector detects the relative position of the reticle grating to the wafer grating. It has been verified that the response sensitivity to the step movements of the wafer was 5 nanometers. The response signals received from various deformed alignment gratings indicated an ideal cosine wave form. The resultant overlay to the irregular surface gratings on an Al deposited wafer was improved to 0.1 µm/3 sigma.

A 10 Bit All-Parallel A/D Converter

This paper describes a 10 bit all-parallel analog-to-digital converter with 20 MHz conversion rate. Static accuracy was achieved by suppressing the offset voltage of pair transistors to be below 0.5 mV, and by laser trimming technology to improve nonlinearity of the dc reference voltages. In regard to dynamic accuracy, an SNR of 53 dB was observed at input signal frequencies up to 1 MHz. A 3 µm bipolar process is adopted, which integrates nearly 40,000 elements onto a 9.2×9.8 mm chip.

A Low Power 8 Bit Parallel A/D Converter with High Accuracy Process

A high accuracy process offering small ΔVBE of pair transistors, small contact resistance, and uniform reference resistance, has been applied in the design of an 8 bit parallel 40 MHz A/D converter. A new bipolar structure produced by serial implantation of B+ and Ass+ through the same opening window of SiO2 has been developed to realize high speed and high uniformity. An optimized high speed comparator stage was developed in which the number of transistors and power consumption were reduced. Consequently, an 800 mW, 40 MHz sampling frequency, 8 bit A/D converter was developed.

Advanced VIST device technology

VIST1)(Vertically Isolated Self-aligned Transistor) Technology and its application to ICs and LSIs are presented. With a walled emitter structure, reduction of the emitter-collector leakage of the VIST, consisting of a birds beak-free oxide-isolated structure and an inactive base (low ρ) self-aligned to the polysilicon emitter, has been made possible. E-C leakage current was measured on a fabricated bipolar integrated circuit array containing one hundred elements/chip. It was found that the thicker the side wall oxide, the remarkably smaller the E-C leakage current became. These results were well corresponded to the density of defects which were observed by Sirtl etching of stripped wafers. Applicability of the VIST to actual device was investigated in a high-speed frequency divider and an 8×8 multiplier/accumulator.

An E-Beam Direct Write Process for 16M-Bit DRAMs

For obtaining a very fine wafer pattern below half micron, direct write EB lithography has charging and proximity effect problems. A method of compensating for the charging problem is to use a 40 kV proton shower irradiation process which decreases the bottom layer resistance of the trilayer resist. The charge of the electron beam is dissipated through the bottom-layer resist. As for the proximity effect, we developed a proximity effect correction software system by dosage modification. The theoretical and experimental results showed that in a 2.2-micron-thick trilayer planarizing resist system, a 0.5-micron isolated line, 0.5-micron isolated space, and 0.5-micron contact holes were simultaneously resolved in a half-micron-thick top-layer resist. The resultant half-micron-rule 16M-bit DRAM patterns were successfully obtained on uneven topography of the processed wafer using EB direct write.

An E-Beam Direct Write Process For Half Micron DRAMS

Direct write electron beam (EB) lithography is expected to write a very fine wafer pattern below half micron for the development of the comming generation ULSIs. But direct write EB lithography has two main peculiar problems for obtaining such a very fine resist pattern on an uneven topography of a processed wafer. One is a pattern dimension deviation from the designed value due to resist topography and proximity effects. The other problem is pattern registration deviation due to charge-up in the EB-resist. In order to investigate the proximity effect. we evaluated the deposited energy density profile by a double gaussian Exposure Intensity Distribution ( EID ) function. The theoretical and experimental results showed that in a 2.2 micron thick trilayer planerizing resist system. both 0.5 micron isolated line and isolated space were simultaneously resolved in half micron thick top layer resist. To compensate the charge-up problem, we treated the bottom-layer by a brand-new ion shower material modification process. A 40 KV proton shower irradiation decreased the resistance of the bottom layer. The charge of the electron beam was dissipated through the bottom layer resist. The resultant half micron rule 16 M-bit DRAM patterns were compared with the optically exposed tri-level resist patterns. The optically exposed patterns also had an optical proximity effect and half micron patterns were not resolved even adopting the contrast enhancement lithographic ( CEL ) technology. On the other hand, we successfully obtained 16M-bit DRAM patterns on the uneven topography of the processed wafer using EB direct write.

Holographic nanometer alignment system for a half-micron wafer stepper

An excellent reticle to wafer overlay accuracy (0.064µm/3σ) was achieved using an holographic nanometer alignment system for a wafer stepper. This alignment system performs as an ideal interferometer using two conjugate beams diffracted from a wafer alignment grating. The remarkable characteristic of the alignment system is the high Signal/Noise ratio which is independent of the surface roughness such as caused by Al deposition. As a result, overlay accuracy was maintained within 0.07µm/3σ on various substrate conditions. Alignment offset caused by the alignment mark deformation was proportional to the asymmetricity of the alignment mark and that is consistent with the calculated results.

High Speed Bipolar ECL Devices Using a Vertically Isolated Self-Aligned Transistor

We have fabricated ECL devices such as ring oscillators and a 1/16 divider to evaluate the performance of a vertically isolated self-aligned transistor which is named VIST. This VIST has a birds beak-free oxide isolation and an inactive base of high impurity concentration formed extremely near the emitter region. Moreover, all the side walls of emitter, base and collector are covered with oxide film. Using VIST, propagation delay time of 160 psec was achieved in an ECL ring oscillator. The ECL divider operated at frequencies up to 2.5 GHz with 21 mW power dissipation per stage. This operating frequency is the highest value ever reported of silicon dividers.

Flat Emitter Transistor with Self-Aligned Base

A flat emitter transistor with a self-aligned base (FLET) has been developed to realize a high speed and low power dissipation bipolar LSI. This FLET has a flat bottom emitter and eliminates parasitic capacitance in the side wall. Accordingly, current gain (hFE) is almost independent of the emitter size and shape. Moreover, high cut-off frequency (fT) and high hFE can be obtained in low current region. The FLET also has an inactive base of high impurity density formed extremely near the emitter region. As a result, the base resistance can be lowered even though single line base structure is used. This base contact structure enables the reduction of CTC and CTS. The divider using FLET operated at frequencies up to 1.3 GHz. The power dissipation was 125 mW, being one fifth that of the conventional divider.