Shuichi Kameyama

High-performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technology

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi/sub 2/ film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L/sub g/ (the physical gate length) is 0.21 mu m for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21- mu m gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5*10/sup 16/ cm/sup -3/). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 mu m, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 mu m. >

A High Integrity and Low Resistance Ti-Polycide Gate Using a Nitrogen Ion-Implanted Buffer Layer

A new titanium-disilicide/polysilicon gate system using a nitrogen ion-implanted buffer layer which has high dielectric strength and low resistivity has been developed. The buffer layer of a nonstoichiometric silicon nitride layer approximately 30 nm-thick is formed with a N2+ dose below 5.0×1016 cm-2 at an acceleration energy of 15 keV. This layer can prevent intermixing of a titanium-disilicide film and a polysilicon film even after high-temperature annealing. Therefore, it can improve dielectric strength without increasing series resistances through those films.