Tadashi Yasufuku

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO

Scaling power supply voltages (VDDs) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower VDD, adaptive VDD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive VDD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed.

A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD

Decreasing power consumption is the key design issue of SSDs. A typical SSD consists of more than 16 NAND Flash memories, DRAMs and a NAND controller. Since the NAND write performance is 10MB/s [1,2], to raise the write speed of SSD to the level of HDD, 100MB/s, 8 or more NAND chips in SSD are simultaneously programmed. As the feature size decreases, the total bitline capacitance in a chip increases beyond 200nF. If 8 or more NAND chips operate in parallel, a large current of 800mA flows to charge the bitline capacitance in a sub-30nm SSD [3]. A good strategy to decrease the power is lowering the supply voltage, VDD, from 3.3 to 1.8V. Yet, at 1.8V, the power consumption of conventional charge pumps, used to generate the 20V program voltage, VPGM, drastically increases and the total power consumption of the NAND does not decrease, as shown in Fig. 13.2.1(a). The charge-pump area more than doubles, which increases the NAND chip area by 5 to 10%. To overcome this problem, we implement a low-power program-voltage generator (PVG) using a boost converter with an adaptive-frequency and duty-cycle (AFD) controller.

Device-circuit interactions in extremely low voltage CMOS designs (invited)

In this paper, energy and minimum operating voltage (VDDmin) are investigated for extremely-low-voltage CMOS logic designs. The dependences of energy and VDDmin on device parameters, such as threshold voltage, subthreshold swing parameter, and DIBL coefficient, are examined based on simulations and measurements.

1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD

In this paper we present an adaptive program-voltage generator for 3D-integrated solid state drives (SSDs) based on a boost converter. The converter consists of a spiral inductor, a high-voltage MOS circuit, and an adaptive-frequency and duty-cycle (AFD) controller. The spiral inductor requires an area of only 5 × 5 mm2 in an interposer. The high-voltage MOS circuit employs a mature NAND flash process. The AFD controller, implemented in a conventional low-voltage MOS process, dynamically optimizes clock frequencies and duty cycles at different values of output voltage, VOUT. The power consumption, rising time, and circuit area of the program-voltage generator are 88%, 73%, and 85% less than those of a program-voltage generator with a conventional charge pump, respectively. The total power consumption of each NAND flash memory is reduced by 68%. We also present the design methodology of the high-voltage MOS circuit of the boost converter with a conventional NAND flash process, in which charge-pump-based program-voltage generators are implemented.

A closed-form expression for estimating minimum operating voltage (V DDmin ) of CMOS logic gates

In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

Stretchable EMI Measurement Sheet With 8

A stretchable 12 × 12 cm2 electromagnetic interference (EMI) measurement sheet is developed to enable the measurement of EMI distribution on the surface of electronic devices by wrapping the devices in the sheet. The sheet consists of an 8 × 8 coil array, a 2 V organic CMOS row decoder and a column selector, 40% stretchable interconnects with carbon nanotubes, and 0.18 μm silicon CMOS circuits for electric and magnetic field detection. The sheet detects the total power of an electric field in the band up to 700 MHz and that of a magnetic field up to 1 GHz. The minimum detectable powers of the electric and magnetic fields are -60 and -70 dBm, respectively.

\times

This paper investigates the effect of the TSV resistance (R<inf>TSV</inf>) on the performance of boost converters for Solid State Drive (SSD) using circuit simulation. When R<inf>TSV</inf> is 0Ω, both the rising time (t<inf>rise</inf>) from 0V to 15V and the energy during boosting (E<inf>loss</inf>) of the output voltage (V<inf>OUT</inf>) are 10.6% and 6.6% of the conventional charge pump respectively. In contrast, when R<inf>TSV</inf> is 200O, for example, t<inf>rise</inf> is 30.1% and E<inf>loss</inf> is 22.8% of the conventional charge pump. Besides, V<inf>OUT</inf> cannot be boosted above 20V when R<inf>TSV</inf> is larger than 210Ω. Therefore, in order to maintain the advantages of the boost converter over the charge pump in terms of t<inf>rise</inf> and E<inf>loss</inf>, the reduction of R<inf>TSV</inf> is very important.

8 Coil Array, 2 V Organic CMOS Decoder, and 0.18

Electromagnetic interference (EMI) is a serious issue degrading the dependability of electronic devices. The issue is complicated by the following technology trends: 1) RF signals and clock pulses of digital ICs are in the same frequency range. 2) The increase of LSI power consumption causes an increase of noise emission. 3) Electronic devices have 3D-structures and packaging is dense. These trends also make the root cause analysis of EMI difficult. For example, it is difficult to find the EMI generation points in electronic devices such as cell-phones and PDAs.

\ \mu

A 3-D solid-state drive system with through-silicon via (TSV) technology and boost converter is presented in this paper. The proposed boost converter enables the supply voltage reduction to 1.8 V and smaller NAND Flash memory chips. From the simulation results, the conventional bonding-wire technology can achieve only eight NAND chip integrations not only due to their structural problem but also due to the performance degradation. On the other hand, 128 NAND Flash memory chips can be integrated into a package with full-copper TSVs and the proposed system has about 1.70 μs of rise time for 20 V, 74.2 nJ of the energy dissipation, and 225 μm2 of additional Si area consumption for a NAND chip. Even if poly-Si TSVs are used, because of the process restriction, 64 NAND chips can be stacked with about 34% longer rise time and 22% degradation of energy dissipation compared to a full-copper TSV by grinding the Si-substrate to 10 μm .

m Silicon CMOS LSIs for Electric and Magnetic Field Detection

Contention-less flip-flops (CLFFs) and separated power supply voltages (VDD) between flip-flops (FFs) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IUs by 64mV on average. By scaling VDD from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved.