Shinji Miyamoto

Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control

Although Self-Aligned Double and Quadruple Patterning (SADP, SAQP) have become the most promising processes for sub-20 nm and sub-14 nm node advanced technologies, not all wafer images are realized by them. In advanced technologies, feasible wafer images should be generated effectively by utilizing SADP and SAQP where a wafer image is uniquely determined by a selected mandrel pattern. However, predicting the wafer image of a mandrel pattern is not easy. In this paper, we propose a routing method of generating a feasible wafer image satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SADP) or three colors (SAQP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, hotspot reduction by dummy pattern flipping is proposed. In experiments, feasible wafer images meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.

A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD

Decreasing power consumption is the key design issue of SSDs. A typical SSD consists of more than 16 NAND Flash memories, DRAMs and a NAND controller. Since the NAND write performance is 10MB/s [1,2], to raise the write speed of SSD to the level of HDD, 100MB/s, 8 or more NAND chips in SSD are simultaneously programmed. As the feature size decreases, the total bitline capacitance in a chip increases beyond 200nF. If 8 or more NAND chips operate in parallel, a large current of 800mA flows to charge the bitline capacitance in a sub-30nm SSD [3]. A good strategy to decrease the power is lowering the supply voltage, VDD, from 3.3 to 1.8V. Yet, at 1.8V, the power consumption of conventional charge pumps, used to generate the 20V program voltage, VPGM, drastically increases and the total power consumption of the NAND does not decrease, as shown in Fig. 13.2.1(a). The charge-pump area more than doubles, which increases the NAND chip area by 5 to 10%. To overcome this problem, we implement a low-power program-voltage generator (PVG) using a boost converter with an adaptive-frequency and duty-cycle (AFD) controller.

A 120mm 2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology

NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.

1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD

In this paper we present an adaptive program-voltage generator for 3D-integrated solid state drives (SSDs) based on a boost converter. The converter consists of a spiral inductor, a high-voltage MOS circuit, and an adaptive-frequency and duty-cycle (AFD) controller. The spiral inductor requires an area of only 5 × 5 mm2 in an interposer. The high-voltage MOS circuit employs a mature NAND flash process. The AFD controller, implemented in a conventional low-voltage MOS process, dynamically optimizes clock frequencies and duty cycles at different values of output voltage, VOUT. The power consumption, rising time, and circuit area of the program-voltage generator are 88%, 73%, and 85% less than those of a program-voltage generator with a conventional charge pump, respectively. The total power consumption of each NAND flash memory is reduced by 68%. We also present the design methodology of the high-voltage MOS circuit of the boost converter with a conventional NAND flash process, in which charge-pump-based program-voltage generators are implemented.

Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories

This paper investigates the effect of the TSV resistance (R<inf>TSV</inf>) on the performance of boost converters for Solid State Drive (SSD) using circuit simulation. When R<inf>TSV</inf> is 0Ω, both the rising time (t<inf>rise</inf>) from 0V to 15V and the energy during boosting (E<inf>loss</inf>) of the output voltage (V<inf>OUT</inf>) are 10.6% and 6.6% of the conventional charge pump respectively. In contrast, when R<inf>TSV</inf> is 200O, for example, t<inf>rise</inf> is 30.1% and E<inf>loss</inf> is 22.8% of the conventional charge pump. Besides, V<inf>OUT</inf> cannot be boosted above 20V when R<inf>TSV</inf> is larger than 210Ω. Therefore, in order to maintain the advantages of the boost converter over the charge pump in terms of t<inf>rise</inf> and E<inf>loss</inf>, the reduction of R<inf>TSV</inf> is very important.

Detailed routing with advanced flexibility and in compliance with self-aligned double patterning constraints

In this paper, we propose a new flexible routing method for Self-Aligned Double Patterning (SADP). SADP is one of the most promising candidates for patterning sub-20 nm node advanced technology but wafer images must satisfy tighter constraints than litho-etch-litho-etch process. Previous SADP routing methods require strict constraints induced from the relation between mandrel and trim patterns, so design freedom is unexpectedly lost. Also these methods assume to form narrow patterns by trimming process without consideration of resolution limit of optical lithography. The proposed method realizes flexible SADP routing with dynamic coloring requiring no decomposition to extract mandrel patterns and no worries about coloring conflicts. The proposed method uses realizable trimming process only for insulation of patterns. The effectiveness of the proposed method is confirmed in the experimental comparisons.

Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories

A 3D-integrated Solid State Drive (SSD) with the boost converter can achieve both the low power and the fast write-operation at the small die area of the NAND flash memory. The performance of the boost converter, however, is critically affected by the inductor, because the output voltage of the boost converter, the rising time, and the energy consumption during the boost are determined by the inductor. Therefore, this paper proposes a design methodology of the inductor of the boost converter for the 3D SSD. By using the boost converter with the optimized inductor, the energy during write-operation of the proposed 1.8-V 3D-SSD is decreased by 68% compared with the conventional 3.3-V 3D-SSD with the charge pump.

A 60% higher write speed, 4.2gbps, 24-channel 3D-Solid State Drive (SSD) with NAND flash channel number detector and intelligent program-voltage booster

The fastest ever 4.2Gbps 3D-Solid State Drive (SSD) with multi-level cell (MLC) NAND flash memories is proposed. The proposed NAND channel number detector automatically detects the number of channels, that is, the number of NAND chips written at the same time. Based on the number of channels, the intelligent program-voltage booster adaptively optimizes the switching clock. As a result, the proposed 3D-SSD realizes both the fastest write and the lowest energy consumption. In the random write with a small data size, the booster operates in an energy saving mode and decreases the energy consumption of the booster by 32%. In the sequential write with a large data size, up to 24 channels are activated. The booster operates in a high-speed mode to accelerate the pumping. The SSD write speed increases by 60%.