Tae-Gyeong Chung

Laser Dicing and Subsequent Die Strength Enhancement Technologies for Ultra-thin Wafer

Current mechanical wafer dicing process adopting diamond grit shows advantages of low cost and high productivity. However, mechanical process for ultra-thin wafers would induce residual stress or mechanical damage, which can lead to wafer broken and die cracking. With the development of laser technology, laser precision micromachining has been employed for thin semiconductor wafer singulation, which shows advantages of no chipping, small kerf width, and high throughput over mechanical blade dicing. However, thermal damage to the chip induced by laser ablation results in die strength degradation. For ultra thin chip, low die strength tends to induce die crack in packaging process. Thus, thermal damage to the chip needs to be studied. In this study, first we made a comparison between mechanical blade sawing and laser ablation processes. Die strength and microstructure changes were studied by means of bending test and transmission electron microscope (TEM) analysis, respectively. Die strength results showed that the die strength obtained by laser dicing was far lower than that obtained by blade sawing. TEM analysis demonstrated that formation of microcracks and porosities in laser diced face, caused the die strength degradation. In addition, significant deviation between frontside and backside die strength was found in the laser micromachinned dies. The reason for this deviation was clarified as the defects density difference existing in top and bottom layer of the chip sidewalk Experiments results showed that the die strength obtained by laser dicing can not meet the demand of the packaging process. It tends to crack or fracture in the die attach or wire bonding process. Thus, it is essential to improve the die strength. Thus, in this investigation, etching processes including wet-etch and dry-etch were attempted to recover the die strength by removing the chip side wall damage. SEM and TEM images indicated that, before etching, the laser diced side walls were with rough surfaces, voids and microcracks. After etching, the surfaces got smooth and most of the voids and microcracks were removed. Chip strength measurement also verified the partial die strength recovery after etching process.

Mechanisms of die and underfill cracking in flip chip PBGA package

This paper focuses on understanding the mechanisms of die and underfill cracking during MRT (Moisture Resistance Test, JEDEC level 3) and TCT (Thermal Cycling Test, -55-125/spl deg/C). A parametric study has been performed to understand the influence of die and substrate thickness, and metal attachment on die cracking. It is found that a combination of thinner die and thicker substrate leads to good results. In the case of metal stiffener attachment on die backside using low modulus adhesive, die cracking is eliminated. Underfill cracking can be categorized into three groups, popcorn cracking, corner cracking, and edge cracking. The popcorn and corner cracking originate from interfacial delamination between underfill and die passivation. Such cracking is improved by baking the organic substrate before the underfill process and by using high adhesion strength underfill. Since the mechanism of underfill edge cracking is very complicated, mechanical simulations and experiments are conducted to understand it. The authors conclude that underfill edge cracking is closely related to the local CTE mismatch between underfill material and silicon die, and can be eliminated by using low CTE underfill material and by control of underfill fillet size.

Improvement of drop reliability in OSP/Cu pad finished packages

This study investigated the improvement of drop reliability of OSP (organic solderability preservatives) pad finished packages having half etched solder ball pads. Besides the effect of the Cu pad etching depth, effects of other factors such as solder composition or reflow peak temperature on drop reliability were examined by the bending impact test and drop test. The bending impact test results showed that the increase of etching depth at the solder ball pad increased the drop reliability because of the fracture mode transition from solder/pad interface failure to solder bulk failure, but that the increase of reflow peak temperature decreased the drop reliability. The drop test results showed that the increase of the etching depth at the solder ball pad increased the drop reliability without the fracture mode transition, and that the change of the solder composition from Sn3.0Ag0.5Cu to Sn1.2Ag0.5Cu0.05Ni increased the drop reliability and shifted the fracture mode from interface failure to the bulk failure. The optimal conditions for the drop reliability improvement are presented in terms of the etching depth at the solder ball pad, the reflow peak temperature, and the solder composition.

Thermal management of high power memory module

In the semiconductor industry, the memory device has not been considered as a high power consuming product. However, the increase in the market requirements for high speed and high density has resulted in memory devices that consume more power. Especially, a memory module accommodated with many high speed memory devices can reach to very high levels of power consumption, which in turn, can reach to very high junction temperatures. Therefore, the devices can not be operated properly without thermal management. Hence, in this paper, we are looking for a way to manage the heat generated in a high power memory module. To achieve this goal, a plate fin type heat sink based on air cooling was adopted with consideration of constraints related to the implementation of its thermal solutions. Then, the cooling capability of the memory module was estimated by a parametric study. The parametric study shows that a 20mm module pitch is necessary to dissipate the amount of heat that is targeted in this paper, which is 30W. With the 20mm module pitch, an optimized heat sink configuration was designed by simulation and the cooling performance of the designed heat sink was validated by experiments. For the experiment, test modules were assembled and the junction temperatures of memory devices mounted on modules was measured on a test board. The results showed that simulated and measured data well correlate with each other within acceptable ranges. The maximum cooling capability of the designed heat sink is 37.1W with a 20mm module pitch

High-performance Substrate Design for DRAM Flip-chip Interconnection using Etch-back Process

To apply an Au-stud bumping, which has the merit of being a supportable fine pad/bump pitch comparable to that of conventional wire-bonding, in the high-reliable, low-cost flip-chip packaging of high-speed DRAMs with a central dual-inline chip pad configuration, a new design method of the flip-chip package substrate was developed. In the method, a narrow, through-center plating line was formed between dual-in-line bump pads, all of which were connected to the central plating line. After thick electroplating of the bump pads for the reliable joint formation between an Au-stud bump and a package substrate, the central plating line was etched out. The Au-stud flip-chip substrate design method was applied to a 512 Mb GDDR4 DRAM, together with the PCB interconnect design to obtain balanced parasitics and improved power delivery, and the resulting 2-layer flip-chip package, showed improved performance, especially, at low supply voltage over the conventional 2-layer BOC package for the device.

Junction-to-top and junction-to-board thermal resistance measurement for 119 BGA packages

Junction-to-top (/spl theta//sub jt/) and junction-to-board (/spl theta//sub jb/) thermal resistance of a 119 BGA package for 4 Mbit SP SRAM have been investigated using the cold plate-Teflon block method and was compared with the junction-to-case thermal resistance (/spl theta//sub jc/) measurement method. Both thermal dice and real dice were prepared to measure the 119 BGA package thermal resistance. The junction-to-case and junction-to-top thermal resistance for a real die are about 3.5/spl deg/C/W and 3.8/spl deg/C/W respectively, whereas with a thermal die, the junction-to-case and junction-to-top thermal resistance are 4.0/spl deg/C/W and 4.8/spl deg/C/W respectively. For both thermal and real die, the junction-to-case thermal resistance is less than the junction-to-top thermal resistance. This is attributed to the different thermal boundary conditions applied to the 119 BGA package for each test method. In the meantime, thermal resistances of packages with thermal dice were approximately 14.3/spl sim/26.3% higher than those of package with real dice, the reason for which is being investigated.

Board level reliability of novel Fan-in package on package(PoP)

The recent requirements for achieving higher memory density in a smaller package size have adopted 3D packaging of thin dies in a single package. However, increasing the number of dies in 3D stacking is limited by increasing the cost due to decrease die stacking yield. The known good package stacking can be solution to overcome such yield loss. In this study, a novel Fan-in PoP solution proposed, stacking two package which have stacked multiple dies each and interconnecting the package through blind EMC via without changing package size. The solder ball of top package fills up the blind EMC via during the reflow process. In order to evaluate the board level reliability, Fan-in PoP(QDP-DSP : Quad Die Package - Dual Stack Package) was mounted to a FR-4 board. Fan-in PoP with various solder compositions wes explored regarding the failure mode, crack propagation and life time under the drop test and thermal cycling test compared to those of ODP (Octa Die Package). The Fan-in PoP showed superior drop performance compared to ODP due to the package flexibility. On the other hand, thennal cycling test results showed a little increased life time compared to ODP. The solder joint formation on the silicon chip through blind EMC via causes the serious thermal stress concentration due to the silicon stiffness.