Se-Yong Oh

Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling

Abstract Growth behavior of tin whiskers from pure tin and tin–bismuth plated leadframe (LF) packages for elevated temperature and high humidity storages and during thermal cycling was observed. In the storage at 60xa0°C/93% relative humidity (RH) and 85xa0°C/85%RH the galvanic corrosion occurred at the outer lead toes and shoulders where the base LF material is exposed, forming tin oxide layers of SnO2. The corroded layers spread inside the film and formed whiskers around the corroded islands. Many whiskers were observed to grow from grain boundaries for the Fe–42Ni alloy (alloy42) LF packages. It was confirmed that the corrosion tends to occur on the side surfaces of outer leads adjacent to the mold flash. The contribution of ionic contaminants in epoxy mold compound (EMC) to the corrosion was not identified. During thermal cycling between −65xa0°C and +150xa0°C whiskers grew out of as-deposited grains for pure tin-plated alloy42 LF packages and they grew linearly with an increase of number of cycle. Growth mechanisms of the whiskers from grain boundaries and as-deposited grains were discussed from the deformation mechanism map for tin and mathematical calculation with a steady-state diffusion model.

Mechanisms of die and underfill cracking in flip chip PBGA package

This paper focuses on understanding the mechanisms of die and underfill cracking during MRT (Moisture Resistance Test, JEDEC level 3) and TCT (Thermal Cycling Test, -55-125/spl deg/C). A parametric study has been performed to understand the influence of die and substrate thickness, and metal attachment on die cracking. It is found that a combination of thinner die and thicker substrate leads to good results. In the case of metal stiffener attachment on die backside using low modulus adhesive, die cracking is eliminated. Underfill cracking can be categorized into three groups, popcorn cracking, corner cracking, and edge cracking. The popcorn and corner cracking originate from interfacial delamination between underfill and die passivation. Such cracking is improved by baking the organic substrate before the underfill process and by using high adhesion strength underfill. Since the mechanism of underfill edge cracking is very complicated, mechanical simulations and experiments are conducted to understand it. The authors conclude that underfill edge cracking is closely related to the local CTE mismatch between underfill material and silicon die, and can be eliminated by using low CTE underfill material and by control of underfill fillet size.

A new efficient equivalent circuit extraction method for multi-port high speed package using multi-input multi-output transmission matrix and polynomial curve fitting

Modem high-speed integrated circuits for multi-gigabit applications require high-density packages with several hundred YO pins, which also require a wideband circuit model of package. Since a wideband model of a multi-port network is generally calculated by a full-wave field solver and given in the form of a scattering parameter, a SPICEcompatible circuit model must be extracted from a scattering matrix. We present the concrete maxtrix formulation for tranforming scattering parameter to transmission matrix for a ZN-port network . This transformation results in a new efficient equivalent circuit extraction method, which conveniently incorporates accurate electromagnetic models of an interconnecting structure including electronic package into a circuit simulator. By using this new exfraction method, we can easily determine the valid bandwidth of an equivalent circuit model .

Reliability of flip chip BGA package on organic substrate

In this paper various reliability issues of the flip chip package on organic substrate, such as the 1st level bump joint reliability, die cracking, underfill cracking, and 2nd level solder ball joint reliabilty, are primarily described. This paper discusses the reasons and resolutions of failures.

Thermal management of high power memory module

In the semiconductor industry, the memory device has not been considered as a high power consuming product. However, the increase in the market requirements for high speed and high density has resulted in memory devices that consume more power. Especially, a memory module accommodated with many high speed memory devices can reach to very high levels of power consumption, which in turn, can reach to very high junction temperatures. Therefore, the devices can not be operated properly without thermal management. Hence, in this paper, we are looking for a way to manage the heat generated in a high power memory module. To achieve this goal, a plate fin type heat sink based on air cooling was adopted with consideration of constraints related to the implementation of its thermal solutions. Then, the cooling capability of the memory module was estimated by a parametric study. The parametric study shows that a 20mm module pitch is necessary to dissipate the amount of heat that is targeted in this paper, which is 30W. With the 20mm module pitch, an optimized heat sink configuration was designed by simulation and the cooling performance of the designed heat sink was validated by experiments. For the experiment, test modules were assembled and the junction temperatures of memory devices mounted on modules was measured on a test board. The results showed that simulated and measured data well correlate with each other within acceptable ranges. The maximum cooling capability of the designed heat sink is 37.1W with a 20mm module pitch

Design of CMOS voltage controlled oscillators using package inductor

This paper presents three different types of CMOS Voltage-Controlled-Oscillators (VCO) with the integration of embedded inductors in a multi-layer package. A high quality (Q) inductor, pertinent to creating an efficient VCO, is easily made with a thick wiring line in a multi-layer package, The embedded inductors are designed with two different packaging technologies. One is a Fine Pitch Ball Grid Array Packaging (FBGA) technology and the other is a Wafer Level Packaging (WLP) technology. The FBGA inductor showed a Q-factor about 60 at the frequency of 2GHz and that of a WLP inductor was about 25 while at 2GHz. The performances of VCOs using embedded inductors were compared with the control, a VCO designed with conventional on-chip inductors. The use of FBGA and WLP created numerous advantages. The Total Figure-Of-Merit (FOM) was enhanced due to not only reduced phase-noises, but also to improved efficiency and tuning range.

Model-order estimation and reduction of distributed interconnects via improved vector fitting

This paper introduces an automated method estimating and reducing the order of macromodel for fast transient simulation. The proposed method improves the vector fitting algorithm for extracting the reduced-order macromodel from the accurate macromodel having redundant poles and residues. The performance of the proposed method has been demonstrated through several test cases.

Passivation cracking mechanism in high density memory devices assembled in SOJ packages adopting LOC die attach technique

The reliability tests were performed for the qualification of the high density memory devices assembled in SOJ (small outline J-leaded) packages utilizing a LOC (lead on chip) die attach technique and it was shown that the functional failure associated with a passivation break took place during T/C (thermal cycling) tests. To give a great insight into the passivation cracking phenomenon, a mechanism related to it was established through stress simulation and it was shown that the double-sided adhesive tape used for the attachment of the leadframe to the chip surface plays a significant role in defining degree of the passivation damage. The effect of the adhesive tape on the passivation damage was experimentally verified. Based on the established mechanism it is also discussed how the physical properties or the dimension of the LOC packaging materials influence the thermomechanical stability of the memory device and a proper design rule is suggested for the improvement of LOC package reliability.

Thermal Characterization of Multi Stack Packages Using Linear Superposition Method

As the mobile products have been developed, many devices of various functions should be packaged into the limited space. Therefore, stacking multi-packages is needed for small form factor. Compared with discrete packages, multi stack packages (MSP) can provide better solutions for power saving, EMI reduction, max frequency up-grade in spite of its higher cost, low test yield, poor quality assurance, and more complicated manufacturing process. But, stacking many packages in confined space has raised concerns related to heat dissipation, which has become one of the most serious problems in the design of MSP. Accordingly, a method to obtain Tj for each chip from the power inputs is needed. This is quite significant at the MSP promotion and design stage, though the temperature value would be changed by system environment. In this paper, a new approach to determine the junction temperatures of the MSP is proposed. The average temperature of the chips was calculated by RSM, and the temperature difference from the average temperature was calculated by linear superposition. Using this approach, one can calculate device junction temperatures simply and accurately

High thermal performance FBGA MCP with a silicon spacer

This paper presents the high thermal performance FBGA MCP (2 chips) using a silicon spacer. When many devices are integrated in a package, they consume much power and raise the junction temperature, so it is important for the package to have high thermal performance. Hence, we designed and developed a high thermal performance FBGA MCP with a silicon spacer that makes additional heat paths. With the silicon spacer, the thermal resistance of junction to ambient is improved by about 15% and the junction to junction is reduced by about 50%. To guarantee the package reliability of the package with the silicon spacer, we performed the reliability test in JEDEC level 3 condition and the package passed the test. The electrical reliability of the package was verified by measuring the diode voltage of the thermal test chip.